component
TS3314PLX
Public Made by Adomby adom
Shenzhen JingYang ESD And Surge Protection (TVS/ESD), SOT-23-5L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TS3314PLX
Shenzhen JingYang · ESD And Surge Protection (TVS/ESD) · SOT-23-5L
TS3314PLX from Shenzhen JingYang, in a SOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O | bidirectional | Protected high-speed data line (one of the four I/O lines in two line pairs) with 3.8 pF typical capacitance and ±30kV air/contact ESD rating per IEC 61000-4-2; the datasheet does not state which I/O number (I/O1 to I/O4) this pin is. |
| 2 | GND | power_in | Ground reference pin; the application note says to connect pin 2 to the system ground plane, and the circuit diagram shows the GND node. |
| 3 | I/O | bidirectional | Protected high-speed data line (one of the four I/O lines in two line pairs) with 3.3V working voltage and 25A (8/20µs) peak pulse current rating; the datasheet does not state which I/O number (I/O1 to I/O4) this pin is. |
| 4 | I/O | bidirectional | Protected high-speed data line (one of the four I/O lines in two line pairs) with 0.1 µA typical leakage at VRWM; the datasheet does not state which I/O number (I/O1 to I/O4) this pin is. |
| 5 | I/O | bidirectional | Protected high-speed data line (one of the four I/O lines in two line pairs) clamped to ground by the TVS array; the datasheet does not state which I/O number (I/O1 to I/O4) this pin is. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Shenzhen JingYang |
| Package | SOT-23-5L |
| Category | Circuit Protection |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Reverse leakage current | IR | 0.1 | 1 | μA | VRWM = 3.3V, T = 25C | 2 | |
| Trigger voltage | Vt1 | 3.5 | 4.2 | 5 | V | It1 = 1mA | 2 |
| Holding voltage | Vh | 1.5 | 3.5 | V | Ih = 90mA | 2 | |
| Clamping voltage | VC | 5.5 | V | IPP = 1A, tp = 8/20μs (Each Line) | 2 | ||
| Clamping voltage | VC | 10 | V | IPP = 10A, tp = 8/20μs (Each Line) | 2 | ||
| Clamping voltage | VC | 16 | V | IPP = 25A, tp = 8/20μs (Each Line) | 2 | ||
| Parasitic capacitance, I/O to ground | CESD | 3.8 | 5 | pF | Between I/O Pins and Ground; VR = 0V, f = 1MHz | 2 | |
| Parasitic capacitance, I/O to I/O | CESD | 2 | 2.5 | pF | Between I/O Pins; VR = 0V, f = 1MHz | 2 | |
| Peak pulse current | IPP | 25 | A | 8/20μs | 2 | ||
| Peak pulse power | PPK | 450 | Watts | 8/20μs | 2 | ||
| ESD withstand voltage (air) | VESD | -30 | 30 | kV | ESD per IEC 61000-4-2 (Air) | 2 | |
| ESD withstand voltage (contact) | VESD | -30 | 30 | kV | ESD per IEC 61000-4-2 (Contact) | 2 | |
| Operating temperature | TOPT | -55 | 125 | C | 2 | ||
| Storage temperature | TSTG | -55 | 150 | C | 2 |
CAD (KiCad official)
- Symbol:
TS3314PLX - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5L (KiCad packages3D, STEP)
- 3D model files:
ts3314plx-etched.step/ts3314plx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ts3314plx.step/ts3314plx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Shenzhen JingYang datasheet (7 pp, sha256
c9c2dc42e009c97d, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TS3314PLX
**Shenzhen JingYang** · ESD And Surge Protection (TVS/ESD) · SOT-23-5L
TS3314PLX from Shenzhen JingYang, in a SOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O | bidirectional | Protected high-speed data line (one of the four I/O lines in two line pairs) with 3.8 pF typical capacitance and ±30kV air/contact ESD rating per IEC 61000-4-2; the datasheet does not state which I/O number (I/O1 to I/O4) this pin is. |
| 2 | GND | power_in | Ground reference pin; the application note says to connect pin 2 to the system ground plane, and the circuit diagram shows the GND node. |
| 3 | I/O | bidirectional | Protected high-speed data line (one of the four I/O lines in two line pairs) with 3.3V working voltage and 25A (8/20µs) peak pulse current rating; the datasheet does not state which I/O number (I/O1 to I/O4) this pin is. |
| 4 | I/O | bidirectional | Protected high-speed data line (one of the four I/O lines in two line pairs) with 0.1 µA typical leakage at VRWM; the datasheet does not state which I/O number (I/O1 to I/O4) this pin is. |
| 5 | I/O | bidirectional | Protected high-speed data line (one of the four I/O lines in two line pairs) clamped to ground by the TVS array; the datasheet does not state which I/O number (I/O1 to I/O4) this pin is. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Shenzhen JingYang |
| Package | SOT-23-5L |
| Category | Circuit Protection |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Reverse leakage current | IR | | 0.1 | 1 | μA | VRWM = 3.3V, T = 25C | 2 |
| Trigger voltage | Vt1 | 3.5 | 4.2 | 5 | V | It1 = 1mA | 2 |
| Holding voltage | Vh | | 1.5 | 3.5 | V | Ih = 90mA | 2 |
| Clamping voltage | VC | | | 5.5 | V | IPP = 1A, tp = 8/20μs (Each Line) | 2 |
| Clamping voltage | VC | | | 10 | V | IPP = 10A, tp = 8/20μs (Each Line) | 2 |
| Clamping voltage | VC | | | 16 | V | IPP = 25A, tp = 8/20μs (Each Line) | 2 |
| Parasitic capacitance, I/O to ground | CESD | | 3.8 | 5 | pF | Between I/O Pins and Ground; VR = 0V, f = 1MHz | 2 |
| Parasitic capacitance, I/O to I/O | CESD | | 2 | 2.5 | pF | Between I/O Pins; VR = 0V, f = 1MHz | 2 |
| Peak pulse current | IPP | | | 25 | A | 8/20μs | 2 |
| Peak pulse power | PPK | | | 450 | Watts | 8/20μs | 2 |
| ESD withstand voltage (air) | VESD | -30 | | 30 | kV | ESD per IEC 61000-4-2 (Air) | 2 |
| ESD withstand voltage (contact) | VESD | -30 | | 30 | kV | ESD per IEC 61000-4-2 (Contact) | 2 |
| Operating temperature | TOPT | -55 | | 125 | C | | 2 |
| Storage temperature | TSTG | -55 | | 150 | C | | 2 |
## CAD (KiCad official)
- Symbol: `TS3314PLX`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5L (KiCad packages3D, STEP)
- 3D model files: `ts3314plx-etched.step` / `ts3314plx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ts3314plx.step` / `ts3314plx.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Shenzhen JingYang datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590412779762192384) (7 pp, sha256 `c9c2dc42e009c97d`, retrieved 2026-10-16, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ts3314plx-datasheet.pdf)