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TRF7960RHBR

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Texas Instruments RF Chips, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TRF7960RHBR

Texas Instruments · RF Chips · VQFN-32-EP(5x5)

TRF7960RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD_A power_out Internal regulated supply output of 2.7 V to 3.4 V for analog circuitry.
2 VIN power_in External supply input to the chip, 2.7 V to 5.5 V.
3 VDD_RF power_out Internal regulated supply of 2.7 V to 5 V, normally connected to VDD_PA (pin 4).
4 VDD_PA power_in Supply for the PA, normally connected externally to VDD_RF (pin 3).
5 TX_OUT output RF output with selectable output power of 100 mW at 8 Ω or 200 mW at 4 Ω with VDD = 5 V.
6 VSS_RF power_in Negative supply for the PA, normally connected to circuit ground.
7 VSS_RX power_in Negative supply for the RX inputs, normally connected to circuit ground.
8 RX_IN1 input RX input used for AM reception.
9 RX_IN2 input RX input used for PM reception.
10 VSS power_in Chip substrate ground.
11 BAND_GAP output Band-gap voltage of 1.6 V serving as internal analog voltage reference, which must be AC-bypassed to ground.
12 ASK/OOK bidirectional Direct mode selects ASK or OOK modulation (0 = ASK, 1 = OOK), and the pin can also be configured to provide the received analog signal output (ANA_OUT).
13 IRQ output Interrupt request output to prompt the MCU for attention.
14 MOD input Direct mode external modulation input.
15 VSS_A power_in Negative supply for internal analog circuits, normally connected to circuit ground.
16 VDD_I/O power_in Supply for I/O communications of 1.8 V to 5.5 V, connected to VIN for 5-V communication or VDD_X for 3.3-V communication.
17 I/O_0 bidirectional I/O pin for parallel communication; tied to VSS or VDD depending on SPI mode selection.
18 I/O_1 bidirectional I/O pin for parallel communication; tied to VDD or VSS depending on SPI mode selection.
19 I/O_2 bidirectional I/O pin for parallel communication; tied to VDD or VSS depending on SPI mode selection.
20 I/O_3 bidirectional I/O pin for parallel communication.
21 I/O_4 bidirectional I/O pin for parallel communication; used as SPI slave select (SS) when SPI with SS is selected.
22 I/O_5 bidirectional I/O pin for parallel communication; serves as strobe out clock for serial communication and data clock output in direct mode.
23 I/O_6 bidirectional I/O pin for parallel communication; serves as MISO for SPI and serial bit data output or subcarrier signal in direct mode.
24 I/O_7 bidirectional I/O pin for parallel communication; serves as MOSI for SPI.
25 EN2 input Pulse enable and selection of power-down mode; if connected to VIN, VDD_X stays active during power down to support the MCU.
26 DATA_CLK input Clock input for MCU communication in parallel and serial modes.
27 SYS_CLK output Clock for the MCU at 3.39, 6.78, or 13.56 MHz when EN = 1, or 60 kHz when EN = 0 and EN2 = 1.
28 EN input Chip enable input; when EN = 0 the chip is in power-down mode.
29 VSS_D power_in Negative supply for internal digital circuits, normally connected to circuit ground.
30 OSC_OUT output Crystal oscillator output.
31 OSC_IN input Crystal oscillator input for the single external 13.56-MHz crystal.
32 VDD_X power_out Internally regulated supply of 2.7 V to 3.4 V for external circuitry such as the MCU.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Radio Frequency Chip/Antenna
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VIN 6 V 8
Output current IO 150 mA 8
Maximum junction temperature TJ 140 °C Any condition 8
Maximum junction temperature TJ 125 °C Continuous operation, long-term reliability 8
Storage temperature range Tstg -55 150 °C 8
Lead temperature 300 °C 1,6 mm (1/16 inch) from case for 10 seconds 8
Supply voltage VIN 2.7 5 5.5 V 8
Operating virtual junction temperature TJ -40 125 °C 8
Operating ambient temperature TA -40 25 110 °C 8
Supply current in power-down mode IPD 1 10 µA All systems disabled, including supply voltage regulators 8
Supply current in power-down mode 2 IPD2 120 300 µA The reference voltage generator and VDD_X remain active to support external circuitry. 8
Supply current in standby mode ISTBY 1.5 4 mA Oscillator running, supply voltage regulators in low-consumption mode 8
Supply current without antenna driver current ION1 10 16 mA Oscillator, regulators, RX, and AGC are active, TX is off 8
Supply current with antenna driver current ION2 70 mA Oscillator, regulators, RX, AGC, and TX are active, Pout = 100 mW 8
Supply current with antenna driver current ION3 120 mA Oscillator, regulators, RX, AGC, and TX are all active, Pout = 200 mW 8
Band-gap voltage BG 1.4 1.6 1.7 V Internal analog reference voltage 8
Power-on-reset voltage VPOR 1.4 2 2.5 V 8
Regulated supply for analog circuitry VDD_A 3.1 3.5 3.8 V 8
Regulated supply for RF circuitry VDD_RF 4 4.6 5.2 V Regulator set for 5-V system with 250-mV difference 9
Regulated supply for external circuitry VDD_X 3.1 3.4 3.8 V 9
Rejection of external supply noise on the supply VDD_RF regulator PPSRR 20 26 dB The difference between the external supply and the regulated voltage is higher than 250 mV, measured at 212 kHz 9
PA driver output resistance RRFOUT 8 12 Ω Half-power mode 9
PA driver output resistance RRFOUT 4 6 Ω Full-power mode 9
RX_IN1 and RX_IN2 input resistance RRFIN 5 10 20 kΩ 9
Maximum input voltage VRFIN 3.5 VPP At RX_IN1 and RX_IN2 inputs 9
Input sensitivity VSENS 1.2 2.5 mVPP fSUBCARRIER = 424 kHz 9
Input sensitivity VSENS 1.2 3 mVPP fSUBCARRIER = 848 kHz 9
Setup time after power down tSET_PD 10 20 ms 9
Setup time after standby mode tSET_STBY 30 100 µs 9
Recovery time after modulation (ISO/IEC 14443) tREC 60 µs Modulation signal: sine, 424 kHz, 10 mVpp 9
SYS_CLK frequency fSYS_CLK 30 60 120 kHz In PD2 mode EN = 0 and EN2 = 1 9
Maximum DATA_CLK frequency fD_CLKmax 2 4 8 MHz Depends on capacitive load on the I/O lines, TI recommends 2 MHz 9
Maximum CLK frequency CLKMAX 2 MHz 9
Input logic low VIL 0.2 ×VDD_I/O 9
Input logic high VIH 0.8 ×VDD_I/O 9
Output resistance of I/O_0 to I/O_7 ROUT 400 800 Ω low_io = H for VDD_I/O < 2.7 V 9
Output resistance of SYS_CLK RSYS_CLK 200 400 Ω low_io = H for VDD_I/O < 2.7 V 9
Junction-to-case thermal resistance (RHB 32) RθJC 31 °C/W 9
Junction-to-ambient thermal resistance (RHB 32) RθJA 36.4 °C/W 9
Power rating (RHB 32) 2.7 W TA ≤ 25°C 9
Power rating (RHB 32) 1.1 W TA = 85°C 9

CAD (KiCad official)

  • Symbol: TRF7960RHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: trf7960rhbr-etched.step / trf7960rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); trf7960rhbr.step / trf7960rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (54 pp, sha256 bcd3653fc5fdb692, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF