# TPUL2T323DR

**Texas Instruments** · Monostable Multivibrators · SOIC-16

TPUL2T323DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1T | input | Channel 1 falling edge trigger input; requires 1T and 1CLR to be held high. |
| 2 | 1T | input | Channel 1 rising edge trigger input; requires 1T to be held low and 1CLR to be held high. |
| 3 | 1CLR | input | Channel 1 asynchronous clear input, active low; also can operate as rising edge trigger input if 1T is held low and 1T is held high. |
| 4 | 1Q | output | Channel 1 inverted output. |
| 5 | 2Q | output | Channel 2 output. |
| 6 | 2C | power_in | Channel 2 external timing capacitor negative connection; provides a return path for discharge current of the external timing capacitor and is internally connected to ground. |
| 7 | 2RC | bidirectional | Channel 2 external timing node connection; see Application Information section for detailed operation instructions. |
| 8 | GND | power_in | Ground. |
| 9 | 2T | input | Channel 2 falling edge trigger input; requires 2T and 2CLR to be held high. |
| 10 | 2T | input | Channel 2 rising edge trigger input; requires 2T to be held low and 2CLR to be held high. |
| 11 | 2CLR | input | Channel 2 asynchronous clear input, active low; also can operate as rising edge trigger input if 2T is held low and 2T is held high. |
| 12 | 2Q | output | Channel 2 inverted output. |
| 13 | 1Q | output | Channel 1 output. |
| 14 | 1C | power_in | Channel 1 external timing capacitor negative connection; provides a return path for discharge current of the external timing capacitor and is internally connected to ground. |
| 15 | 1RC | bidirectional | Channel 1 external timing node connection; see Application Information section for detailed operation instructions. |
| 16 | VCC | power_in | Positive voltage supply. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive switching threshold | VT+ | 0.65 | 0.84 | 0.96 | V | VCC = 1.5V | 5 |
| Positive switching threshold | VT+ | 0.73 | 0.95 | 1.11 | V | VCC = 1.8V | 5 |
| Positive switching threshold | VT+ | 0.88 | 1.11 | 1.33 | V | VCC = 2.5V | 5 |
| Positive switching threshold | VT+ | 1.03 | 1.27 | 1.5 | V | VCC = 3.3V | 5 |
| Positive switching threshold | VT+ | 1.33 | 1.58 | 1.82 | V | VCC = 5V | 5 |
| Positive switching threshold | VT+ | 1.41 | 1.67 | 1.91 | V | VCC = 5.5V | 5 |
| Negative switching threshold | VT- | 0.32 | 0.41 | 0.5 | V | VCC = 1.5V | 5 |
| Negative switching threshold | VT- | 0.36 | 0.46 | 0.53 | V | VCC = 1.8V | 5 |
| Negative switching threshold | VT- | 0.45 | 0.55 | 0.63 | V | VCC = 2.5V | 5 |
| Negative switching threshold | VT- | 0.54 | 0.65 | 0.74 | V | VCC = 3.3V | 5 |
| Negative switching threshold | VT- | 0.7 | 0.85 | 0.96 | V | VCC = 5V | 5 |
| Negative switching threshold | VT- | 0.74 | 0.89 | 1.02 | V | VCC = 5.5V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.33 | 0.45 | 0.6 | V | VCC = 1.5V | 6 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.36 | 0.5 | 0.65 | V | VCC = 1.8V | 6 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.42 | 0.56 | 0.72 | V | VCC = 2.5V | 6 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.49 | 0.62 | 0.78 | V | VCC = 3.3V | 6 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.61 | 0.74 | 0.91 | V | VCC = 5V | 6 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.65 | 0.77 | 0.95 | V | VCC = 5.5V | 6 |
| High-level output voltage | VOH | 1.2 | 1.61 |  | V | IOH = -1mA, VCC = 1.65V | 6 |
| High-level output voltage | VOH | 2.1 | 2.24 |  | V | IOH = -2mA, VCC = 2.3V | 6 |
| High-level output voltage | VOH | 2.4 | 2.78 |  | V | IOH = -8mA, VCC = 3V | 6 |
| High-level output voltage | VOH | 3.94 | 4.21 |  | V | IOH = -12mA, VCC = 4.5V | 6 |
| High-level output voltage | VOH | 4.94 | 5.23 |  | V | IOH = -12mA, VCC = 5.5V | 6 |
| Low-level output voltage | VOL |  | 0.03 | 0.45 | V | IOL = 1mA, VCC = 1.65V | 6 |
| Low-level output voltage | VOL |  | 0.04 | 0.2 | V | IOL = 2mA, VCC = 2.3V | 6 |
| Low-level output voltage | VOL |  | 0.13 | 0.4 | V | IOL = 8mA, VCC = 3V | 6 |
| Low-level output voltage | VOL |  | 0.15 | 0.5 | V | IOL = 12mA, VCC = 4.5V | 6 |
| Low-level output voltage | VOL |  | 0.13 | 0.5 | V | IOL = 12mA, VCC = 5.5V | 6 |
| Input leakage current | II | -50 |  | 50 | nA | VI = 5.5V or 0V; VCC 0V to 5.5V | 6 |
| Capacitor pin current, monitor state | ICEXT | -50 |  | 50 | nA | Monitor state, VCEXT = 0.5 × VCC; VCC 1.5V to 5.5V | 6 |
| Capacitor pin current, active discharging | ICEXT | 11 |  |  | mA | Active state, discharging, VCEXT = 1.5V, VCC = 1.5V | 6 |
| Capacitor pin current, active discharging | ICEXT | 29 |  |  | mA | Active state, discharging, VCEXT = 2.3V, VCC = 2.3V | 6 |
| Capacitor pin current, active discharging | ICEXT | 45 |  |  | mA | Active state, discharging, VCEXT = 3V, VCC = 3V | 6 |
| Capacitor pin current, active discharging | ICEXT | 95 |  |  | mA | Active state, discharging, VCEXT = 4.5V, VCC = 4.5V | 6 |
| Capacitor pin current, active discharging | ICEXT | 138 |  |  | mA | Active state, discharging, VCEXT = 5.5V, VCC = 5.5V | 6 |
| Partial power-off current | Ioff |  | 0.25 | 10 | µA | VI or VO = 5.5V or 0V; VCC 0V to 0.3V | 6 |
| Supply current, ready state | ICC |  | 0.19 | 2 | µA | Ready state, VI = VCC or 0V, IO = 0; VCC = 5.5V | 6 |
| Supply-current change per input | ΔICC |  |  | 2.1 | mA | One input VI = 0 to VCC, other inputs at VCC or 0V, IO = 0mA; VCC 1.5V to 5.5V | 7 |
| Supply current, active per channel, comparator enabled, 10MHz clock | ICC |  |  | 275 | µA | Active state per channel, internal analog comparator enabled, 10MHz clock, VI = VCC or 0V, IO = 0; VCC = 1.5V | 7 |
| Supply current, active per channel, comparator enabled, 10MHz clock | ICC |  |  | 315 | µA | Active state per channel, internal analog comparator enabled, 10MHz clock, VI = VCC or 0V, IO = 0; VCC = 1.65V | 7 |
| Supply current, active per channel, comparator enabled, 10MHz clock | ICC |  |  | 375 | µA | Active state per channel, internal analog comparator enabled, 10MHz clock, VI = VCC or 0V, IO = 0; VCC = 2.3V | 7 |
| Supply current, active per channel, comparator enabled, 10MHz clock | ICC |  |  | 560 | µA | Active state per channel, internal analog comparator enabled, 10MHz clock, VI = VCC or 0V, IO = 0; VCC = 3V | 7 |
| Supply current, active per channel, comparator enabled, 10MHz clock | ICC |  |  | 1020 | µA | Active state per channel, internal analog comparator enabled, 10MHz clock, VI = VCC or 0V, IO = 0; VCC = 4.5V | 7 |
| Supply current, active per channel, comparator enabled, 10MHz clock | ICC |  |  | 1370 | µA | Active state per channel, internal analog comparator enabled, 10MHz clock, VI = VCC or 0V, IO = 0; VCC = 5.5V | 7 |
| Recommended supply voltage | VCC | 1.5 |  | 5.5 | V |  | 4 |
| Input voltage | VI | 0 |  | 5.5 | V |  | 4 |
| External timing resistance | Rext | 6.5 |  | 1000 | kΩ | VCC = 1.5V to 5.5V | 5 |
| External timing capacitance | Cext | 0.1 |  | 1000 | nF | VCC = 1.5V to 5.5V | 5 |
| Configured output pulse width | two | 0.01 |  | 880 | s | VCC = 1.5V to 5.5V | 5 |
| Digital output load capacitance | CL |  |  | 50 | pF | VCC = 1.5V to 5.5V | 5 |
| Power-on reset ramp voltage | VPOR | 0.3 |  | 1.5 | V | Δt/ΔVCC ≥ 20µs/V | 5 |
| Operating free-air temperature | TA | -40 |  | 125 | °C |  | 5 |
| Supply voltage range | VCC | -0.5 |  | 6.5 | V |  | 4 |
| Digital input voltage range | VI | -0.5 |  | 6.5 | V |  | 4 |
| Digital output current, continuous | IO | -50 |  | 50 | mA | VO = 0 to VCC | 4 |
| Continuous current through VCC or GND |  | -200 |  | 200 | mA |  | 4 |
| Junction temperature | TJ |  |  | 150 | °C |  | 4 |
| Junction-to-ambient thermal resistance (D, SOIC-16) | RθJA |  | 112.3 |  | °C/W | D (SOIC) 16 pins | 5 |
| Junction-to-case (top) thermal resistance (D, SOIC-16) | RθJC(top) |  | 73.9 |  | °C/W | D (SOIC) 16 pins | 5 |
| Output pulse width error (Δtwo) | Δtwo | -10 | 1 | 10 | % | CL = 50pF; VCC = 1.5V to 5.5V; excludes timing component variation | 10 |

## CAD (KiCad official)

- Symbol: `TPUL2T323DR`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `tpul2t323dr-etched.step` / `tpul2t323dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpul2t323dr.step` / `tpul2t323dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tpul2t323.pdf) (52 pp, sha256 `7d1471a3ed2a96b9`, retrieved 2026-10-19, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tpul2t323dr-datasheet.pdf)