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docs tptlv70033ddcr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json tptlv70033ddcr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC b… · Ray
README.md tptlv70033ddcr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
tptlv70033ddcr-etched.fit.json tptlv70033ddcr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
tptlv70033ddcr-etched.glb tptlv70033ddcr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC b… · Ray
tptlv70033ddcr-etched.step tptlv70033ddcr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC b… · Ray
tptlv70033ddcr.glb Publish 0.1.0 · Ray
tptlv70033ddcr.kicad_mod Publish 0.1.0 · Ray
tptlv70033ddcr.kicad_sym Publish 0.1.0 · Ray
tptlv70033ddcr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
tptlv70033ddcr.step Publish 0.1.0 · Ray

TPTLV70033DDCR

TECH PUBLIC · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPTLV70033DDCR from TECH PUBLIC, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Input supply voltage. Operating range 1.2V to 5.5V (absolute max 6.5V to GND). Bypass with a 1µF to 10µF ceramic capacitor close to the pin.
2 GND power_in Device ground reference and return path for the regulator. Typical ground/quiescent current is 20µA at no load.
3 EN input Enable control input. Drive above VENH (typ 0.7V, max 0.9V) to enable the regulator; drive below VENL (typ 0.65V, min 0.4V) to shut down. Absolute max 6V to GND; input leakage ~0.1µA at 5.5V. Do not leave floating.
4 NC unconnected No internal connection. Leave floating or tie to GND on the PCB.
5 VOUT power_out Regulated output of the LDO. Fixed 3.3V (this ordering suffix) at up to 300mA, ±1.5% accuracy. Requires a 1µF to 10µF ceramic output capacitor. Includes an internal ~80Ω active-discharge path to GND when disabled.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOT-23-5
Category PMIC
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • TPTLV70033DDCR

CAD (KiCad official)

  • Symbol: TPTLV70033DDCR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tptlv70033ddcr-etched.step / tptlv70033ddcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tptlv70033ddcr.step / tptlv70033ddcr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tptlv70033ddcr.step 85 KB You want the bare part, or you mark your own boards.
tptlv70033ddcr-etched.step 2.3 MB You want the part with TPTLV70033DDCR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 574 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (10 pp, sha256 c627377631f68455, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF