component
TPT4031-TS3R
Public Made by Adomby adom
3PEAK RS-485 / RS-422 ICs, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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TPT4031-TS3R
3PEAK · RS-485 / RS-422 ICs · TSSOP-16
TPT4031-TS3R from 3PEAK, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1D | input | Driver 1 logic input, with VIH of at least 2.0 V and VIL of at most 0.8 V (Table 4). |
| 2 | 1Y | output | Driver 1 non-inverted bus output, which follows 1D when the driver is enabled (Table 12). |
| 3 | 1Z | output | Driver 1 inverted bus output, which is complementary to 1Y when the driver is enabled (Table 12). |
| 4 | G | input | Active-high enable input: the drivers are enabled when G is high, and the outputs go high-impedance when G is low and /G is high (Table 12). |
| 5 | 2Z | output | Driver 2 inverted bus output, which is complementary to 2Y when the driver is enabled (Table 12). |
| 6 | 2Y | output | Driver 2 non-inverted bus output, which follows 2D when the driver is enabled (Table 12). |
| 7 | 2D | input | Driver 2 logic input, with VIH of at least 2.0 V and VIL of at most 0.8 V (Table 4). |
| 8 | GND | power_in | Ground pin for the device. |
| 9 | 3D | input | Driver 3 logic input, with VIH of at least 2.0 V and VIL of at most 0.8 V (Table 4). |
| 10 | 3Y | output | Driver 3 non-inverted bus output, which follows 3D when the driver is enabled (Table 12). |
| 11 | 3Z | output | Driver 3 inverted bus output, which is complementary to 3Y when the driver is enabled (Table 12). |
| 12 | /G | input | Active-low enable input: the drivers are enabled when /G is low (Table 12). |
| 13 | 4Z | output | Driver 4 inverted bus output, which is complementary to 4Y when the driver is enabled (Table 12). |
| 14 | 4Y | output | Driver 4 non-inverted bus output, which follows 4D when the driver is enabled (Table 12). |
| 15 | 4D | input | Driver 4 logic input, with VIH of at least 2.0 V and VIL of at most 0.8 V (Table 4). |
| 16 | VCC | power_in | Power supply pin, with an operating range of 3.0 V to 5.5 V (Table 5). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 3PEAK |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (VI) lower limit | VI | -0.5 | V | Printed max is VCC + 0.5 V (not numeric) | 5 | ||
| Supply voltage | VCC | -0.5 | 7 | V | 5 | ||
| Output voltage | VO | -0.5 | 7 | V | 5 | ||
| Input or output clamp current | IIK, IOK | -20 | 20 | mA | 5 | ||
| Output current | IO | -150 | 150 | mA | 5 | ||
| VCC current | 200 | mA | 5 | ||||
| GND current | -200 | mA | 5 | ||||
| Operating virtual junction temperature | TJ | 150 | °C | 5 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| Supply voltage | VCC | 3 | 5.5 | V | 5 | ||
| High-level input voltage (driver, driver enable) | VIH | 2 | V | Printed max is VCC (not numeric) | 5 | ||
| Low-level input voltage (driver, driver enable) | VIL | 0 | 0.8 | V | 5 | ||
| Differential load resistance | RL | 100 | Ω | 5 | |||
| Operating ambient temperature | TA | -40 | 125 | °C | 5 | ||
| Enable-input clamp voltage | VIK | -1.5 | V | IO = 18 mA | 7 | ||
| Logic input high voltage | VIH | 2 | V | Dx, G, /G | 7 | ||
| Logic input low voltage | VIL | 0.8 | V | Dx, G, /G | 7 | ||
| Input current | II | -10 | 10 | uA | VI = VCC or GND | 7 | |
| Driver output current with power off | IO(off) | 6 | 50 | uA | VCC=0, VO = 6 V | 7 | |
| Driver output current with power off | IO(off) | -50 | -6 | uA | VCC=0, VO = -0.25 V | 7 | |
| Driver output short-circuit current | IOS | -150 | -30 | mA | Bus pin Y, Z short current | 7 | |
| High-impedance off-state output current | IOZ | 20 | uA | VO = 6 V | 7 | ||
| High-impedance off-state output current | IOZ | -100 | uA | VO = -0.25 V | 7 | ||
| Change in magnitude of VOD | Δ/VOD/ | -0.4 | 0 | 0.4 | V | RL = 100 Ω, see Figure 1 | 7 |
| Change in magnitude of VOC | Δ/VOC/ | -0.4 | 0 | 0.4 | V | RL = 100 Ω, see Figure 1 | 7 |
| High-level output voltage | VOH | 2.4 | 4.6 | V | VCC = 5.0 V; IO = -20 mA | 7 | |
| Low-level output voltage | VOL | 0.21 | 0.4 | V | VCC = 5.0 V; IO = 20 mA | 7 | |
| Differential output voltage magnitude | VOD | 2.4 | 3.9 | V | VCC = 5.0 V; RL = 100 Ω, see Figure 1 | 7 | |
| Differential output voltage magnitude | VOD | 4 | 5 | V | VCC = 5.0 V; No load, see Figure 1 | 7 | |
| Common-mode output voltage | VOC | 2.35 | 3 | V | VCC = 5.0 V; RL = 100 Ω, see Figure 1 | 7 | |
| Quiescent supply current | ICC | 30 | 50 | uA | VCC = 5.0 V; IO=0, VI = 0 or 5 V | 7 | |
| Quiescent supply current | ICC | 20 | 40 | uA | VCC = 3.3 V; IO=0, VI = 0 or 3.3 V | 9 | |
| Propagation delay time, low-to-high-level output | tPLH | 3 | 8 | 12 | ns | VCC = 5.0 V; SW is open, see Figure 2 | 8 |
| Propagation delay time, high-to-low-level output | tPHL | 3 | 8 | 12 | ns | VCC = 5.0 V; SW is open, see Figure 2 | 8 |
| Pulse skew time (/tPLH, tPHL/) | tsk(p) | 0.5 | 5 | ns | VCC = 5.0 V; SW is open, see Figure 2 | 8 | |
| Differential output rise time | tr | 6.5 | 10 | ns | VCC = 5.0 V; SW is open, see Figure 2 | 8 | |
| Differential output fall time | tf | 6.5 | 10 | ns | VCC = 5.0 V; SW is open, see Figure 2 | 8 | |
| Output enable time to high level | tPZH | 12 | 20 | ns | VCC = 5.0 V; SW is closed, see Figure 3 | 8 | |
| Output enable time to low level | tPZL | 14 | 20 | ns | VCC = 5.0 V; SW is closed, see Figure 3 | 8 | |
| Output disable time from high level | tPHZ | 9 | 20 | ns | VCC = 5.0 V; SW is closed, see Figure 3 | 8 | |
| Output disable time from low level | tPLZ | 10 | 17 | ns | VCC = 5.0 V; SW is closed, see Figure 3 | 8 | |
| Output enable time to high level | tPZH | 13.5 | 23 | ns | VCC = 3.3 V; SW is closed, see Figure 3 | 9 | |
| Output enable time to low level | tPZL | 16.5 | 23 | ns | VCC = 3.3 V; SW is closed, see Figure 3 | 9 | |
| Output disable time from high level | tPHZ | 11 | 23 | ns | VCC = 3.3 V; SW is closed, see Figure 3 | 9 | |
| Output disable time from low level | tPLZ | 14 | 23 | ns | VCC = 3.3 V; SW is closed, see Figure 3 | 9 | |
| Junction-to-ambient thermal resistance (TSSOP) | θJA | 115 | °C/W | 16-Pin TSSOP; 1S0P PCB per JEDEC | 6 | ||
| Junction-to-case thermal resistance (TSSOP) | θJC | 48 | °C/W | 16-Pin TSSOP; 1S0P PCB per JEDEC | 6 |
CAD (KiCad official)
- Symbol:
TPT4031-TS3R - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
tpt4031-ts3r-etched.step/tpt4031-ts3r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpt4031-ts3r.step/tpt4031-ts3r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 3PEAK datasheet (19 pp, sha256
40d7dd28e47e9dc8, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).