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TPT29555-TS5R

Public Made by Adom

by adom

3PEAK I/O Expanders, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPT29555-TS5R

3PEAK · I/O Expanders · TSSOP-24

TPT29555-TS5R from 3PEAK, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INT output Open-drain active-LOW interrupt output that must be connected to VCC through a pull-up resistor.
2 A1 input Address input 1; connect directly to VCC or ground to set the fixed I2C-bus address.
3 A2 input Address input 2; connect directly to VCC or ground to set the fixed I2C-bus address.
4 P00 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
5 P01 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
6 P02 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
7 P03 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
8 P04 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
9 P05 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
10 P06 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
11 P07 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
12 GND power_in Ground reference for the device.
13 P10 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
14 P11 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
15 P12 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
16 P13 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
17 P14 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
18 P15 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
19 P16 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
20 P17 bidirectional P-port I/O with push-pull structure, configured as an input at power-on and with an internal weak pull-up.
21 A0 input Address input 0; connect directly to VCC or ground to set the fixed I2C-bus address.
22 SCL input Serial clock bus; connect to VCC through a pull-up resistor.
23 SDA bidirectional Serial data bus; connect to VCC through a pull-up resistor.
24 VCC power_in Supply voltage; recommended operating range is 1.65 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer 3PEAK
Package TSSOP-24
Category Interface
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Supply voltage VCC -0.5 6 V 5
VI Input voltage VI -0.5 6 V 5
VO Output voltage VO -0.5 6 V 5
Input-output clamp current IIOK -20 20 mA VO < 0 or VO > VCC 5
Continuous output low current IOL 50 mA VO = 0 to VCC 5
Continuous output high current IOH -50 mA VO = 0 to VCC 5
Continuous current through GND ICC -250 mA 5
Maximum Junction Temperature TJ 150 °C 5
Operating Temperature Range TA -45 85 °C 5
Supply voltage VCC 1.65 5.5 V 6
High-level input voltage, A2-A0, P07-P00, P17-P10 VIH 5.5 V 6
Low-level input voltage, SCL, SDA VIL -0.5 mA 6
Low-level input voltage, A2-A0, P07-P00, P17-P10 VIL -0.5 mA 6
High-level output current, P07-P00, P17-P10 IOH -10 mA 6
Low-level output current, P07-P00, P17-P10 IOL 25 mA 6
Low-level output current, INT, SDA IOL 6 mA 6
Input clamping voltage VIK -1.2 V II = -18 mA 7
Power-on reset voltage VPOR 1.2 1.4 V VI = VDD or VSS; IO = 0 mA 7
LOW-level output current, SDA IOL 3 mA VOL = 0.4 V; VDD = 1.65 V to 5.5 V 7
LOW-level output current, INT IOL 3 mA 7
LOW-level output current, P port IOL 8 mA VOL = 0.5 V; VDD = 1.65 V 7
LOW-level output current, P port IOL 10 mA VOL = 0.7 V; VDD = 1.65 V 7
LOW-level output current, P port IOL 12 mA VOL = 0.5 V; VDD = 2.3 V 7
LOW-level output current, P port IOL 15 mA VOL = 0.7 V; VDD = 2.3 V 7
LOW-level output current, P port IOL 20 mA VOL = 0.5 V; VDD = 3.0 V 7
LOW-level output current, P port IOL 30 mA VOL = 0.5 V; VDD = 4.5 V 7
HIGH-level output voltage, P port VOH 1.3 V IOH = -8 mA; VDD = 1.65 V 7
HIGH-level output voltage, P port VOH 1.25 V IOH = -10 mA; VDD = 1.65 V 7
HIGH-level output voltage, P port VOH 2 V IOH = -8 mA; VDD = 2.3 V 7
HIGH-level output voltage, P port VOH 1.95 V IOH = -10 mA; VDD = 2.3 V 7
HIGH-level output voltage, P port VOH 2.8 V IOH = -8 mA; VDD = 3.0 V 7
HIGH-level output voltage, P port VOH 2.75 V IOH = -10 mA; VDD = 3.0 V 7
HIGH-level output voltage, P port VOH 4.3 V IOH = -8 mA; VDD = 4.5 V 7
HIGH-level output voltage, P port VOH 4.25 V IOH = -10 mA; VDD = 4.5 V 7
LOW-level output voltage, P port VOL 0.35 V P port; IOL = 8 mA; VDD = 1.65 V 7
LOW-level output voltage, P port VOL 0.3 V P port; IOL = 8 mA; VDD = 2.3 V 7
LOW-level output voltage, P port VOL 0.25 V P port; IOL = 8 mA; VDD = 3.0 V 7
LOW-level output voltage, P port VOL 0.2 V P port; IOL = 8 mA; VDD = 4.5 V 7
Input current, SCL, SDA, RESET II -1 uA VDD = 1.65 V to 5.5 V; VI = VDD or VSS 7
Input current, A0, A1, A2 II -1 uA VDD = 1.65 V to 5.5 V; VI = VDD or VSS 7
HIGH-level input current, P port IIH 1 uA VI = VDD; VDD = 1.65 V to 5.5 V 7
LOW-level input current, P port IIL -100 uA VI = VSS; VDD = 1.65 V to 5.5 V 7
Supply current, operating, fSCL = 400 kHz IDD 25 uA VI on SDA = VDD or VSS; VI on P port and A0-A2 = VDD; IO = 0 mA; I/O = inputs; fSCL = 400 kHz; VDD = 3.6 V to 5.5 V 7
Supply current, operating, fSCL = 400 kHz IDD 15 uA VI on SDA = VDD or VSS; VI on P port and A0-A2 = VDD; IO = 0 mA; I/O = inputs; fSCL = 400 kHz; VDD = 2.3 V to 3.6 V 7
Supply current, operating, fSCL = 400 kHz IDD 9 uA VI on SDA = VDD or VSS; VI on P port and A0-A2 = VDD; IO = 0 mA; I/O = inputs; fSCL = 400 kHz; VDD = 1.65 V to 2.3 V 7
Supply current, fSCL = 0 kHz IDD 3 7 uA VI on SCL, SDA = VDD or VSS; VI on P port and A0-A2 = VDD; IO = 0 mA; I/O = inputs; fSCL = 0 kHz; VDD = 3.6 V to 5.5 V 8
Supply current, fSCL = 0 kHz IDD 2 3.2 uA VI on SCL, SDA = VDD or VSS; VI on P port and A0-A2 = VDD; IO = 0 mA; I/O = inputs; fSCL = 0 kHz; VDD = 2.3 V to 3.6 V 8
Supply current, fSCL = 0 kHz IDD 1 1.7 uA VI on SCL, SDA = VDD or VSS; VI on P port and A0-A2 = VDD; IO = 0 mA; I/O = inputs; fSCL = 0 kHz; VDD = 1.65 V to 2.3 V 8
Supply current, active mode, continuous register read IDD 60 125 uA VI on P port, A0-A2 = VDD; IO = 0 mA; I/O = inputs; fSCL = 400 kHz; VDD = 3.6 V to 5.5 V 8
Supply current, active mode, continuous register read IDD 40 75 uA VI on P port, A0-A2 = VDD; IO = 0 mA; I/O = inputs; fSCL = 400 kHz; VDD = 2.3 V to 3.6 V 8
Supply current, active mode, continuous register read IDD 20 45 uA VI on P port, A0-A2 = VDD; IO = 0 mA; I/O = inputs; fSCL = 400 kHz; VDD = 1.65 V to 2.3 V 8
Supply current, pull-ups enabled IDD 1.1 1.5 mA VI on SCL and SDA = VDD or VSS; VI on P port = VSS; VI on A0-A2 = VDD or VSS; IO = 0 mA; I/O = inputs with pull-up enabled; fSCL = 0 kHz; VDD = 1.65 V to 5.5 V 8
Additional quiescent supply current, SCL, SDA ⊿IDD 25 uA one input at VDD -0.6 V, other inputs at VDD or VSS; VDD = 1.65 V to 5.5 V 8
Additional quiescent supply current, P port, A0-A2 ⊿IDD 80 uA one input at VDD -0.6 V, other inputs at VDD or VSS; VDD = 1.65 V to 5.5 V 8
Input capacitance Ci 6 7 pF VI = VDD or VSS; VDD = 1.65 V to 5.5 V 8
Input/output capacitance Cio 7 8 pF VI/O = VDD or VSS; VDD = 1.65 V to 5.5 V 8
Junction-to-ambient thermal resistance, TSSOP24 θJA 110 °C/W 6
Junction-to-case thermal resistance, TSSOP24 θJC 60 °C/W 6

CAD (KiCad official)

  • Symbol: TPT29555-TS5R
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: tpt29555-ts5r-etched.step / tpt29555-ts5r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpt29555-ts5r.step / tpt29555-ts5r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: 3PEAK datasheet (14 pp, sha256 b93f386b21b8ab7e, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF