component
TPSRDA05-6
Public Made by Adomby adom
TECH PUBLIC ESD And Surge Protection (TVS/ESD), SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
TPSRDA05-6
TECH PUBLIC · ESD And Surge Protection (TVS/ESD) · SOP-8
TPSRDA05-6 from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O 1 | passive | ESD/surge protected I/O line 1, steered by diodes to +VREF and GND (5 V working voltage, 5 pF max to GND). |
| 2 | I/O 2 | passive | ESD/surge protected I/O line 2, steered by diodes to +VREF and GND (5 V working voltage, 5 pF max to GND). |
| 3 | +VREF | passive | Reference rail of the steering-diode array to which the I/O clamp diodes connect, with reverse working voltage 5.0 V max. |
| 4 | I/O 3 | passive | ESD/surge protected I/O line 3, steered by diodes to +VREF and GND (5 V working voltage, 5 pF max to GND). |
| 5 | I/O 4 | passive | ESD/surge protected I/O line 4, steered by diodes to +VREF and GND (5 V working voltage, 5 pF max to GND). |
| 6 | I/O 5 | passive | ESD/surge protected I/O line 5, steered by diodes to +VREF and GND (5 V working voltage, 5 pF max to GND). |
| 7 | I/O 6 | passive | ESD/surge protected I/O line 6, steered by diodes to +VREF and GND (5 V working voltage, 5 pF max to GND). |
| 8 | GND | power_in | Ground reference for the TVS array; ESD rated ±30 kV air/contact per IEC 61000-4-2. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOP-8 |
| Category | Circuit Protection |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TPSRDA05-6 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
tpsrda05-6-etched.step/tpsrda05-6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpsrda05-6.step/tpsrda05-6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TECH PUBLIC datasheet (4 pp, sha256
9ad5a7413537dd60, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPSRDA05-6
**TECH PUBLIC** · ESD And Surge Protection (TVS/ESD) · SOP-8
TPSRDA05-6 from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O 1 | passive | ESD/surge protected I/O line 1, steered by diodes to +VREF and GND (5 V working voltage, 5 pF max to GND). |
| 2 | I/O 2 | passive | ESD/surge protected I/O line 2, steered by diodes to +VREF and GND (5 V working voltage, 5 pF max to GND). |
| 3 | +VREF | passive | Reference rail of the steering-diode array to which the I/O clamp diodes connect, with reverse working voltage 5.0 V max. |
| 4 | I/O 3 | passive | ESD/surge protected I/O line 3, steered by diodes to +VREF and GND (5 V working voltage, 5 pF max to GND). |
| 5 | I/O 4 | passive | ESD/surge protected I/O line 4, steered by diodes to +VREF and GND (5 V working voltage, 5 pF max to GND). |
| 6 | I/O 5 | passive | ESD/surge protected I/O line 5, steered by diodes to +VREF and GND (5 V working voltage, 5 pF max to GND). |
| 7 | I/O 6 | passive | ESD/surge protected I/O line 6, steered by diodes to +VREF and GND (5 V working voltage, 5 pF max to GND). |
| 8 | GND | power_in | Ground reference for the TVS array; ESD rated ±30 kV air/contact per IEC 61000-4-2. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOP-8 |
| Category | Circuit Protection |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `TPSRDA05-6`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `tpsrda05-6-etched.step` / `tpsrda05-6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpsrda05-6.step` / `tpsrda05-6.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TECH PUBLIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604422942008750080) (4 pp, sha256 `9ad5a7413537dd60`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tpsrda05-6-datasheet.pdf)