main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 17d ago
viewers tpsms12ct1g: viewers · Ray 17d ago
package.json Publish 0.1.0 · Ray 17d ago
page.json Set visibility: public · Ray 17d ago
README.md Publish 0.1.0 · Ray 17d ago
tpsms12ct1g-etched.glb Publish 0.1.0 · Ray 17d ago
tpsms12ct1g-etched.step tpsms12ct1g: factory component page (tier=lcsc) · Ray 17d ago
tpsms12ct1g-hero.glb tpsms12ct1g: hero GLB from the etched model (keeps the MPN mark) · Ray 17d ago
tpsms12ct1g-hero.overlay.json Publish 0.1.0 · Ray 17d ago
tpsms12ct1g.glb Publish 0.1.0 · Ray 17d ago
tpsms12ct1g.kicad_mod Publish 0.1.0 · Ray 17d ago
tpsms12ct1g.kicad_sym Publish 0.1.0 · Ray 17d ago
tpsms12ct1g.lbr Publish 0.1.0 · Ray 17d ago
tpsms12ct1g.step Publish 0.1.0 · Ray 17d ago

TPSMS12CT1G

TECH PUBLIC · ESD And Surge Protection (TVS/ESD) · SOT-23-6

TPSMS12CT1G from TECH PUBLIC, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I/O1 passive Protected I/O line (diode cathode in the schematic) with 12V max reverse working voltage to ground and 60pF max capacitance to GND.
2 GND power_in Common ground/reference node of the array, to which all I/O pins are clamped, tied to the center node in the schematic.
3 I/O2 passive Protected I/O line with 12V max reverse working voltage to ground, ±30kV IEC 61000-4-2 air/contact ESD rating.
4 I/O3 passive Protected I/O line with 12V max reverse working voltage to ground and 1uA max leakage at VRWM.
5 I/O4 passive Protected I/O line (diode cathode toward the center node in the schematic) with 12V max reverse working voltage to ground and 30pF max between I/O pins.
6 I/O5 passive Protected I/O line with 12V max reverse working voltage, 12A peak pulse current (8/20µs) and 30V max clamping at 12A.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOT-23-6
Category Circuit Protection
Pins 6

CAD (KiCad official)

  • Symbol: TPSMS12CT1G
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: tpsms12ct1g-etched.step / tpsms12ct1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpsms12ct1g.step / tpsms12ct1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (4 pp, sha256 dba712615a854feb, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF