component
TPSI4202DY-T1-GE3
Public Made by Adomby adom
TECH PUBLIC MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPSI4202DY-T1-GE3
TECH PUBLIC · MOSFETs · SOP-8
TPSI4202DY-T1-GE3 from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of MOSFET 1; VDS max 30 V, continuous drain current 10 A at TA=25C. |
| 2 | G1 | input | Gate of MOSFET 1; gate-source voltage limit ±20 V, threshold 1 V min to 3 V max. |
| 3 | S2 | passive | Source of MOSFET 2; VDS max 30 V, continuous drain current 10 A at TA=25C. |
| 4 | G2 | input | Gate of MOSFET 2; gate-source voltage limit ±20 V, threshold 1 V min to 3 V max. |
| 5 | D2 | passive | Drain of MOSFET 2 (pins 5 and 6 tied together); VDS max 30 V, RDS(on) 16 mOhm max at VGS=10V. |
| 6 | D2 | passive | Drain of MOSFET 2 (pins 5 and 6 tied together); VDS max 30 V, RDS(on) 16 mOhm max at VGS=10V. |
| 7 | D1 | passive | Drain of MOSFET 1 (pins 7 and 8 tied together); VDS max 30 V, RDS(on) 16 mOhm max at VGS=10V. |
| 8 | D1 | passive | Drain of MOSFET 1 (pins 7 and 8 tied together); VDS max 30 V, RDS(on) 16 mOhm max at VGS=10V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TPSI4202DY-T1-GE3 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
tpsi4202dy-t1-ge3-etched.step/tpsi4202dy-t1-ge3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpsi4202dy-t1-ge3.step/tpsi4202dy-t1-ge3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TECH PUBLIC datasheet (5 pp, sha256
f40826fedd0a0121, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPSI4202DY-T1-GE3
**TECH PUBLIC** · MOSFETs · SOP-8
TPSI4202DY-T1-GE3 from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of MOSFET 1; VDS max 30 V, continuous drain current 10 A at TA=25C. |
| 2 | G1 | input | Gate of MOSFET 1; gate-source voltage limit ±20 V, threshold 1 V min to 3 V max. |
| 3 | S2 | passive | Source of MOSFET 2; VDS max 30 V, continuous drain current 10 A at TA=25C. |
| 4 | G2 | input | Gate of MOSFET 2; gate-source voltage limit ±20 V, threshold 1 V min to 3 V max. |
| 5 | D2 | passive | Drain of MOSFET 2 (pins 5 and 6 tied together); VDS max 30 V, RDS(on) 16 mOhm max at VGS=10V. |
| 6 | D2 | passive | Drain of MOSFET 2 (pins 5 and 6 tied together); VDS max 30 V, RDS(on) 16 mOhm max at VGS=10V. |
| 7 | D1 | passive | Drain of MOSFET 1 (pins 7 and 8 tied together); VDS max 30 V, RDS(on) 16 mOhm max at VGS=10V. |
| 8 | D1 | passive | Drain of MOSFET 1 (pins 7 and 8 tied together); VDS max 30 V, RDS(on) 16 mOhm max at VGS=10V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `TPSI4202DY-T1-GE3`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `tpsi4202dy-t1-ge3-etched.step` / `tpsi4202dy-t1-ge3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpsi4202dy-t1-ge3.step` / `tpsi4202dy-t1-ge3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TECH PUBLIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603063117496795136) (5 pp, sha256 `f40826fedd0a0121`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tpsi4202dy-t1-ge3-datasheet.pdf)