component
TPSI3050SDWZR
Public Made by Adomby adom
Texas Instruments Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPSI3050SDWZR
Texas Instruments · Gate Drivers · SOIC-8
TPSI3050SDWZR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Active high driver enable, rated 0 to 48 V in two-wire mode and 0 to 5.5 V in three-wire mode (with respect to VSSP). |
| 2 | PXFR | input | An external resistor from PXFR to VSSP selects one of seven power transfer levels, setting the converter duty cycle in three-wire mode or the EN current limit in two-wire mode; the power transfer control input is rated 0 to 5.5 V. |
| 3 | VDDP | power_in | Primary side supply, 3.0 to 5.5 V in three-wire mode (with respect to VSSP), with 0.22 to 20 µF decoupling to VSSP. |
| 4 | VSSP | power_in | Ground supply for the primary side, the reference for the primary-side voltages (EN, PXFR, VDDP). |
| 5 | VSSS | power_in | Ground supply for the secondary side, the reference for the secondary-side voltages (VDRV, VDDH, VDDM). |
| 6 | VDDM | power_out | Generated mid supply on the secondary side, absolute maximum 6 V with respect to VSSS, with 0.003 to 40 µF decoupling across VDDM and VSSS. |
| 7 | VDDH | power_out | Generated high supply on the secondary side, absolute maximum 12 V with respect to VSSS, with VDDH to VDDM limited to 6 V and 0.003 to 40 µF decoupling across VDDH and VDDM. |
| 8 | VDRV | output | Active high driver output for the external power switch, absolute maximum 12 V with respect to VSSS, providing a nominal 10 V gate drive with 1.5/3.0 A peak source and sink current. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Motor Driver ICs |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TPSI3050SDWZR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tpsi3050sdwzr-etched.step/tpsi3050sdwzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpsi3050sdwzr.step/tpsi3050sdwzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (42 pp, sha256
b5a23c997554bf6e, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPSI3050SDWZR
**Texas Instruments** · Gate Drivers · SOIC-8
TPSI3050SDWZR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Active high driver enable, rated 0 to 48 V in two-wire mode and 0 to 5.5 V in three-wire mode (with respect to VSSP). |
| 2 | PXFR | input | An external resistor from PXFR to VSSP selects one of seven power transfer levels, setting the converter duty cycle in three-wire mode or the EN current limit in two-wire mode; the power transfer control input is rated 0 to 5.5 V. |
| 3 | VDDP | power_in | Primary side supply, 3.0 to 5.5 V in three-wire mode (with respect to VSSP), with 0.22 to 20 µF decoupling to VSSP. |
| 4 | VSSP | power_in | Ground supply for the primary side, the reference for the primary-side voltages (EN, PXFR, VDDP). |
| 5 | VSSS | power_in | Ground supply for the secondary side, the reference for the secondary-side voltages (VDRV, VDDH, VDDM). |
| 6 | VDDM | power_out | Generated mid supply on the secondary side, absolute maximum 6 V with respect to VSSS, with 0.003 to 40 µF decoupling across VDDM and VSSS. |
| 7 | VDDH | power_out | Generated high supply on the secondary side, absolute maximum 12 V with respect to VSSS, with VDDH to VDDM limited to 6 V and 0.003 to 40 µF decoupling across VDDH and VDDM. |
| 8 | VDRV | output | Active high driver output for the external power switch, absolute maximum 12 V with respect to VSSS, providing a nominal 10 V gate drive with 1.5/3.0 A peak source and sink current. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Motor Driver ICs |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `TPSI3050SDWZR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `tpsi3050sdwzr-etched.step` / `tpsi3050sdwzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tpsi3050sdwzr.step` / `tpsi3050sdwzr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604371479094181888) (42 pp, sha256 `b5a23c997554bf6e`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tpsi3050sdwzr-datasheet.pdf)