component
TPSI3050QDWZRQ1
Public Made by Adomby adom
Texas Instruments Motor Driver ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPSI3050QDWZRQ1
Texas Instruments · Motor Driver ICs · SOIC-8
TPSI3050QDWZRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Active-high driver enable, recommended 0 to 48.0 V in two-wire mode and 0 to 5.5 V in three-wire mode (absolute maximum 60 V). |
| 2 | PXFR | input | Power transfer control: an external resistor from PXFR to VSSP selects one of seven power levels, setting the power-converter duty cycle in three-wire mode or the EN pin current limit in two-wire mode (0 to 5.5 V recommended, 60 V absolute maximum). |
| 3 | VDDP | power_in | Primary-side power supply, 3.0 to 5.5 V in three-wire mode (6 V absolute maximum), referenced to VSSP. |
| 4 | VSSP | power_in | Ground supply for the primary side. |
| 5 | VSSS | power_in | Ground supply for the secondary side. |
| 6 | VDDM | power_out | Generated mid supply, referenced to VSSS (6 V absolute maximum), with 0.003 to 40 µF decoupling to VSSS. |
| 7 | VDDH | power_out | Generated high supply (nominal 10 V gate-drive rail, 12 V absolute maximum), with 0.003 to 40 µF decoupling to VDDM. |
| 8 | VDRV | output | Active-high driver output with 1.5/3-A peak source and sink current (12 V absolute maximum). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Supply Chip |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDDP undervoltage threshold rising | VVDDP_UV_R | 2.5 | 2.7 | 2.9 | V | VDDP rising | 8 |
| VDDP undervoltage threshold falling | VVDDP_UV_F | 2.35 | 2.55 | 2.75 | V | VDDP falling | 8 |
| VDDH undervoltage threshold rising | VVDDH_UV_R | 8.3 | 8.6 | 9 | V | VDDH rising. | 8 |
| VDDH undervoltage threshold falling | VVDDH_UV_F | 6.3 | 6.6 | 6.9 | V | TPSI3050-Q1 only. VDDH falling. | 8 |
| VDDH output voltage, two-wire | VVDDH | 9.4 | 10.2 | 11 | V | EN = 6.5 V, VVDDH in steady state. | 9 |
| VDRV output voltage driven high, two-wire | VVDRV_H | 9.4 | 10.2 | 11 | V | EN = 6.5 V, VVDDH in steady state, no DC loading. | 9 |
| VDDM voltage sourcing external current, two-wire | VVDDM_IAUX | 4.6 | 5.5 | V | EN = 6.5 V, steady state. RPXFR = 20 kΩ, CDIV1 = CDIV2 = 220 nF, source 1.7 mA from VDDM, measure VDDM voltage. | 9 | |
| VDDH output voltage, three-wire | VVDDH | 9.4 | 10.2 | 11 | V | VVDDP = 3.0 V, EN = 3.0 V, VVDDH in steady state. | 10 |
| VDRV output voltage driven high, three-wire | VVDRV_H | 9.4 | 10.2 | 11 | V | VVDDP = 3.0 V, EN = 3.0 V, VVDDH in steady state, no DC loading. | 10 |
| VDDM voltage sourcing external current, three-wire | VVDDM_IAUX | 4.6 | 5.5 | V | VVDDP = 5.0 V, EN = 0 V, steady state, RPXFR = 20 kΩ, CDIV1 = CDIV2 = 220 nF, source 10 mA from VDDM, measure VVDDM. | 10 | |
| Minimum EN voltage for valid logic high, two-wire | VIH_EN | 6.5 | V | Two-wire mode | 8 | ||
| Maximum EN voltage for valid logic low, two-wire | VIL_EN | 2 | V | Two-wire mode | 9 | ||
| VDDP output voltage ripple | VVDDP_RIPPLE | 600 | mV | EN = 6.5 V, VVDDH in steady state. | 9 | ||
| VDRV output voltage driven low | VVDRV_L | 0.1 | V | EN = 6.5 V → 0 V, VVDDH in steady state, sink 10 mA load. | 9 | ||
| Propagation delay EN falling to VDRV 10%, two-wire | tHL_VDRV | 2.4 | 3 | µs | EN = 6.5 V → 0 V, VVDRV = 1.0 V. | 11 | |
| Propagation delay EN rising to VDRV 90%, three-wire | tLH_VDRV | 3 | 4.5 | µs | VVDDP = 3.3 V, VVDDH steady state, EN = 0 V → 3.3 V, VVDRV = 9.0 V. | 11 | |
| Propagation delay EN falling to VDRV 10%, three-wire | tHL_VDRV | 2.5 | 3 | µs | VVDDP = 3.3 V, VVDDH steady state, EN = 3.3 V → 0 V, VVDRV = 1.0 V. | 11 | |
| VDDP primary supply voltage, three-wire | VDDP | 3 | 5.5 | V | Three-wire mode | 5 | |
| Enable voltage, two-wire | EN | 0 | 48 | V | Two-wire mode | 5 | |
| Enable voltage, three-wire | EN | 0 | 5.5 | V | Three-wire mode | 5 | |
| Power transfer control voltage | PXFR | 0 | 5.5 | V | 5 | ||
| Decoupling capacitance VDDP-VSSP, two-wire | CVDDP | 220 | 330 | nF | Two-wire mode | 5 | |
| Decoupling capacitance VDDP-VSSP, three-wire | CVDDP | 0.22 | 20 | µF | Three-wire mode | 5 | |
| Decoupling capacitance VDDH-VDDM | CDIV1 | 0.003 | 40 | µF | 5 | ||
| Decoupling capacitance VDDM-VSSS | CDIV2 | 0.003 | 40 | µF | 5 | ||
| Ambient operating temperature | TA | -40 | 125 | °C | 5 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| EN rise and fall rate, two-wire | /ΔVEN/Δt/ | 65 | V/ms | Two-wire mode | 5 | ||
| VDDP voltage | VDDP | -0.3 | 6 | V | 5 | ||
| EN voltage | EN | -0.3 | 60 | V | 5 | ||
| PXFR voltage | PXFR | -0.3 | 60 | V | 5 | ||
| VDRV voltage | VDRV | -0.3 | 12 | V | 5 | ||
| VDDH voltage | VDDH | -0.3 | 12 | V | 5 | ||
| VDDM voltage | VDDM | -0.3 | 6 | V | 5 | ||
| VDDH, VDDM voltage | VDDH, VDDM | -0.3 | 6 | V | 5 | ||
| Junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RϴJA | 89.3 | °C/W | DWZ (SOIC) 8 pins | 6 | ||
| Junction-to-case (top) thermal resistance | RϴJC(top) | 40.3 | °C/W | DWZ (SOIC) 8 pins | 6 | ||
| Junction-to-board thermal resistance | RΘJB | 45.2 | °C/W | DWZ (SOIC) 8 pins | 6 | ||
| Junction-to-top characterization parameter | ψJT | 10.3 | °C/W | DWZ (SOIC) 8 pins | 6 | ||
| Junction-to-board characterization parameter | ΨJB | 44.4 | °C/W | DWZ (SOIC) 8 pins | 6 | ||
| Maximum power dissipation, VDDP | PD | 250 | mW | VVDDP = 5 V, RPXFR = 20 kΩ, three-wire mode, CVDRV = 100 pF, CDIV1 = CDIV2 = 100 nF, fEN = 1-kHz square wave, VEN = 5 V peak to peak. | 6 | ||
| Maximum power dissipation, EN | PD | 350 | mW | RPXFR = 20 kΩ, two-wire mode, CVDRV = 100 pF, CDIV1 = CDIV2 = 100 nF, fEN = 1-kHz square wave, VEN = 48 V peak to peak. | 6 | ||
| VDDP undervoltage threshold hysteresis | VVDDP_UV_HYS | 75 | mV | 8 | |||
| Temperature shutdown | TSD | 173 | ℃ | 8 | |||
| VDDH undervoltage threshold hysteresis | VVDDH_UV_HYS | 2 | V | TPSI3050-Q1 only. | 8 | ||
| Driver on resistance in low state | RDSON_VDRV | 1.7 | Ω | Force VVDDH = 10 V, sink IVDRV = 50 mA. | 8 | ||
| Driver on resistance in high state | RDSON_VDRV | 2.5 | Ω | Force VVDDH = 10 V, source IVDRV = 50 mA. | 8 | ||
| VDRV peak output current during rise | IVDRV_PEAK | 1.5 | A | VVDDH in steady state, transition EN from low to high, measure peak current. | 8 | ||
| VDRV peak output current during fall | IVDRV_PEAK | 3 | A | VVDDH in steady state, transition EN from high to low, measure peak current. | 8 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pet | Reinforced insulation; Maximum transient isolation voltage, 7071 VPK; Maximum repetitive peak isolation voltage, 1414 VPK; Maximum | 7 | |
| contacts | copper | pins to maximize thermal conductivity. However, keep in mind that no traces or coppers from different high | 34 |
CAD (KiCad official)
- Symbol:
TPSI3050QDWZRQ1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tpsi3050qdwzrq1-etched.step/tpsi3050qdwzrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpsi3050qdwzrq1.step/tpsi3050qdwzrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (44 pp, sha256
507738bfe65bca19, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).