# TPS990STPZPQ1

**Texas Instruments** · Power Management Specialized - PMIC · LQFP-100(14x14)

TPS990STPZPQ1 from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ENB_1P1V | output | External 1.1V buck enable output, which provides a 3.3V output level. |
| 2 | ENB_1P8V | output | External 1.8V buck enable output, which provides a 3.3V output level. |
| 3 | ENB_3P3V | output | External 3.3V buck enable output, which provides a 3.3V output level. |
| 4 | ADC_MISO | output | ADC 2-wire interface data output between the DLPC23xS-Q1 (primary) and the TPS99000S-Q1 (secondary). |
| 5 | ADC_MOSI | input | ADC 2-wire interface data input between the DLPC23xS-Q1 (primary) and the TPS99000S-Q1 (secondary); absolute maximum is -0.3 V to 3.6 V to ground. |
| 6 | WD1 | input | Watchdog interrupt channel 1 input. |
| 7 | WD2 | input | Watchdog interrupt channel 2 input. |
| 8 | PARK_Z | output | DMD mirror parking signal, active low. |
| 9 | RESET_Z | output | Reset output to the DLPC23xS-Q1, controlled by the TPS99000S-Q1. |
| 10 | INT_Z | output | Open-drain interrupt output to the DLPC23xS-Q1; recommended to be pulled up to the DLPC23xS-Q1 3.3V rail controlled by the ENB_3P3V signal, with an absolute maximum of 7.5 V. |
| 11 | PROJ_ON | input | Input signal to enable or disable the IC and the DLP projector. |
| 12 | COMPOUT | output | Photodiode (PD) interface high-speed comparator output, which requires trace capacitance of 20 pF typical and 50 pF maximum. |
| 13 | VSS_IO | power_in | Ground connection for the digital IO interface. |
| 14 | VDD_IO | power_in | 3.3V power input for the IO rail supply; absolute maximum is 4 V relative to VSS_IO. |
| 15 | SYNC | output | External LED buck driver sync strobe output. |
| 16 | SEQ_START | input | PWM shadow latch control input that indicates the start of a sequence; requires a 10 kΩ pulldown to avoid a floating input at power-up and power-down. |
| 17 | SEQ_CLK | input | Sequencer clock input with a 30 MHz clock rate; requires a 10 kΩ pulldown to avoid a floating input at power-up and power-down. |
| 18 | D_EN | input | LED interface buck high-side FET drive enable input; requires a 10 kΩ pulldown or direct tie to ground when not connected to the DLPC23xS-Q1. |
| 19 | S_EN | input | LED bypass shunt strobe input; requires a 10 kΩ pulldown or direct tie to ground when not connected to the DLPC23xS-Q1. |
| 20 | LED_SEL_0 | input | LED enable strobe 0 input; requires a 10 kΩ pulldown or direct tie to ground when not connected to the DLPC23xS-Q1. |
| 21 | LED_SEL_1 | input | LED enable strobe 1 input; requires a 10 kΩ pulldown or direct tie to ground when not connected to the DLPC23xS-Q1. |
| 22 | LED_SEL_2 | input | LED enable strobe 2 input; requires a 10 kΩ pulldown or direct tie to ground when not connected to the DLPC23xS-Q1. |
| 23 | LED_SEL_3 | input | LED enable strobe 3 input; requires a 10 kΩ pulldown or direct tie to ground when not connected to the DLPC23xS-Q1. |
| 24 | DVSS | power_in | Digital core ground return. |
| 25 | PBKG | power_in | Substrate tie and ESD ground return. |
| 26 | DVDD | power_in | 3.3V power input for the digital core supply. |
| 27 | SPI1_CLK | input | SPI control interface clock input (DLPC23xS-Q1 primary, TPS99000S-Q1 secondary), up to 30 MHz; requires a 10 kΩ pulldown. |
| 28 | SPI1_SS_Z | input | SPI control interface chip select input, active low (DLPC23xS-Q1 primary, TPS99000S-Q1 secondary). |
| 29 | SPI1_DOUT | output | SPI control interface transmit data output (DLPC23xS-Q1 primary, TPS99000S-Q1 secondary). |
| 30 | SPI1_DIN | input | SPI control interface receive data input (DLPC23xS-Q1 primary, TPS99000S-Q1 secondary); requires a 10 kΩ pulldown. |
| 31 | SPI2_DIN | input | SPI diagnostic port (secondary) receive data input for read-only monitoring; requires a 10 kΩ pulldown. |
| 32 | SPI2_DOUT | output | SPI diagnostic port (secondary) transmit data output for read-only monitoring. |
| 33 | SPI2_SS_Z | input | SPI diagnostic port (secondary) chip select input, active low, for read-only monitoring. |
| 34 | SPI2_CLK | input | SPI diagnostic port (secondary) clock input for read-only monitoring, up to 30 MHz; requires a 10 kΩ pulldown. |
| 35 | VSS_IO | power_in | Ground connection for the digital IO interface. |
| 36 | VDD_IO | power_in | 3.3V power input for the IO rail supply. |
| 37 | EXT_SMPL | input | Reserved; connect to ground. Absolute maximum is -0.3 V to 3.6 V to ground. |
| 38 | DRV_EN | output | Drive enable output for the LM3409 LED driver. |
| 39 | CMODE | output | Capacitor selection output that allows a smaller capacitance in CM mode for less overshoot or undershoot; open drain. |
| 40 | DMUX0 | output | Digital test point output. |
| 41 | DMUX1 | output | Digital test point output. |
| 42 | DRVR_PWR | power_in | 6 V or 3.3 V power input for FET driver power, supplying the S_EN1, S_EN2, R_EN, G_EN, and B_EN outputs; absolute maximum is 7.5 V to ground. |
| 43 | S_EN1 | output | Low resistance shunt NFET drive enable output; high means shunt active. |
| 44 | S_EN2 | output | High resistance shunt NFET drive enable output; high means shunt active. |
| 45 | R_EN | output | Red channel select output that drives the low side NFET. |
| 46 | G_EN | output | Green channel select output that drives the low side NFET. |
| 47 | B_EN | output | Blue channel select output that drives the low side NFET. |
| 48 | VSS_DRVR | power_in | Ground connection for FET driver power. |
| 49 | DMD_VOFFSET | power_out | VOFFSET output rail; connect a 1 µF ceramic capacitor to ground and provide a 0.1 mA to 1 mA pulldown load. |
| 50 | DMD_VBIAS | power_out | VBIAS output rail; connect a 0.47 µF ceramic capacitor to ground and provide a 0.1 mA to 1 mA pulldown load. |
| 51 | DMD_VRESET | power_out | VRESET output rail; connect a 1 µF ceramic capacitor to ground and connect to DRST_HS_IND through an external diode with the anode on DMD_VRESET. |
| 52 | DRST_LS_IND | passive | Connection for the DMD power supply inductor (10 µH); connect a 330 pF, 50 V X7R capacitor to ground. |
| 53 | DRST_PGND | power_in | Power ground for the DMD power supply; connect to the ground plane. |
| 54 | DRST_HS_IND | passive | Connection for the DMD power supply inductor (10 µH). |
| 55 | VIN_DRST | power_in | 6 V input for the DMD power supply; absolute maximum is 7.5 V to ground. |
| 56 | VSS_DRST | power_in | Ground supply for the DMD power supply. |
| 57 | AMUX1 | output | Analog test mux output 1. |
| 58 | VMAIN | input | Main intermediate voltage monitor input; an external resistor divider sets the voltage for brownout monitoring; absolute maximum is 7.5 V. |
| 59 | AVDD | power_in | 3.3V power supply input for the analog circuit. |
| 60 | PBKG | power_in | Substrate tie and ESD ground return. |
| 61 | AMUX0 | output | Analog test mux output 0. |
| 62 | VIN_LDOT_M8 | output | Dedicated TIA interface -8V LDO external regulation FET drive signal; absolute range is -18 V to 0.3 V to ground. |
| 63 | VLDOT_M8 | power_out | Dedicated TIA interface -8V LDO output. |
| 64 | VLDOT_5V | power_out | Filter cap interface for the 5V TIA LDO. |
| 65 | VIN_LDOT_5V | power_in | 6 V power input for the 5V TIA LDO; absolute maximum is 7.5 V to ground. |
| 66 | GND_LDO | power_in | Power ground return for the LDO. |
| 67 | VIN_LDOT_3P3V | power_in | 6 V power input for the 3.3V TIA LDO; absolute maximum is 7.5 V to ground. |
| 68 | VLDOT_3P3V | power_out | Filter cap interface for the 3.3V TIA LDO. |
| 69 | TIA_PD2_FILT | output | TIA2 external filter cap for low bandwidth sampling. |
| 70 | TIA_PD2 | input | TIA2 photodiode cathode driver input; it is a noise-sensitive real-time analog input. |
| 71 | VSS_TIA2 | power_in | TIA2 dedicated ground. |
| 72 | VSS_TIA1 | power_in | TIA1 dedicated ground. |
| 73 | TIA_PD1 | input | TIA1 photodiode cathode driver input; it is a noise-sensitive real-time analog input. |
| 74 | TIA_PD1_FILT | output | TIA1 external filter cap for low bandwidth sampling. |
| 75 | PBKG | power_in | Substrate tie and ESD ground return. |
| 76 | R_IADJ | passive | External resistance for IADJ voltage-to-current transformation; absolute maximum is 5 V to ground. |
| 77 | IADJ | passive | Current output used to adjust the external LED controller drive current set point; absolute maximum is 18 V to ground. |
| 78 | AVSS | power_in | Analog ground. |
| 79 | VIN_LDOA_3P3 | power_in | 6 V power input for the dedicated ADC interface 3.3V LDO supply; absolute maximum is 7.5 V to ground. |
| 80 | VLDOA_3P3 | power_out | Dedicated ADC interface 3.3V LDO filter cap output. |
| 81 | VSSL_ADC | power_in | External ADC channel bondwire and lead frame isolation ground. |
| 82 | LS_SENSE_N | input | Low side current sense ADC negative input; absolute range is -0.3 V to 3.6 V to ground. |
| 83 | LS_SENSE_P | input | Low side current sense ADC positive input; absolute range is -0.3 V to 3.6 V to ground. |
| 84 | VSSL_ADC | power_in | External ADC channel bondwire and lead frame isolation ground. |
| 85 | ADC_IN1 | input | External ADC channel 1 input; absolute range is -0.3 V to 3.6 V to ground. |
| 86 | ADC_IN2 | input | External ADC channel 2 input; absolute range is -0.3 V to 3.6 V to ground. |
| 87 | VSSL_ADC | power_in | External ADC channel bondwire and lead frame isolation ground. |
| 88 | ADC_IN3 | input | External ADC channel 3 input; absolute range is -0.3 V to 3.6 V to ground. |
| 89 | VSSL_ADC | power_in | External ADC channel bondwire and lead frame isolation ground. |
| 90 | ADC_IN4 | input | External ADC channel 4 input; absolute range is -0.3 V to 3.6 V to ground. |
| 91 | VSSL_ADC | power_in | External ADC channel bondwire and lead frame isolation ground. |
| 92 | ADC_IN5 | input | External ADC channel 5 input; absolute range is -0.3 V to 3.6 V to ground. |
| 93 | ADC_IN6 | input | External ADC channel 6 input; absolute range is -0.3 V to 3.6 V to ground. |
| 94 | ADC_IN7 | input | External ADC channel 7 input; absolute range is -0.3 V to 3.6 V to ground. |
| 95 | ADC_VREF | power_out | ADC reference voltage output. |
| 96 | V3P3V | input | External 3.3V buck voltage monitor input; absolute maximum is 5 V to ground. |
| 97 | V1P8V | input | External 1.8V buck voltage monitor input; absolute maximum is 5 V to ground. |
| 98 | V1P1V | input | External 1.1V buck voltage monitor input; absolute maximum is 5 V to ground. |
| 99 | PBKG | power_in | Substrate tie and ESD ground return. |
| 100 | AVSS | power_in | Analog ground. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-100(14x14) |
| Category | Power Supply Chip |
| Pins | 100 |

## CAD (KiCad official)

- Symbol: `TPS990STPZPQ1`
- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`
- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files: `tps990stpzpq1-etched.step` / `tps990stpzpq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps990stpzpq1.step` / `tps990stpzpq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps99000s-q1) (86 pp, sha256 `2bba38c5dae6164d`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps990stpzpq1-datasheet.pdf)