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TPS92682QRHBRQ1

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Texas Instruments LED Drivers, QFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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TPS92682QRHBRQ1

Texas Instruments · LED Drivers · QFN-32(5x5)

TPS92682QRHBRQ1 from Texas Instruments, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in High-voltage input (4.5V minimum during battery crank, 6.5V to 65V normal operation) to internal LDO.
2 EN input Hardware enable input; pull low to enter shutdown mode.
3 PWM1 input External PWM signal input to enable PWM dimming for channel-1.
4 PWM2 input External PWM signal input to enable PWM dimming for channel-2.
5 SSN input SPI chip select input, active low.
6 SCK input SPI clock input for serial communication.
7 MISO output SPI slave data output for serial communication.
8 MOSI input SPI slave data input for serial communication.
9 LH input Digital input; set high to enter limp-home mode with independent SPI configuration registers.
10 FLT1 tri_state Open-drain fault output for channel-1 (or both channels if pin-11 programmed as SYNC); must be pulled high externally.
11 FLT2/SYNC bidirectional Dual-function pin (programmable) as either open-drain fault output for channel-2 or external SYNC clock input.
12 COMP2 bidirectional Connect to integral or integral-proportional compensation network to ensure stability for channel-2.
13 PDRV2 output Channel-2 P-channel gate driver output; connect to gate of external series P-channel FET switch.
14 CSN2 input High-side current sense amplifier negative input (-) for channel-2.
15 CSP2 input High-side current sense amplifier positive input (+) for channel-2; accepts 0V to 60V common-mode voltage.
16 FB2/OV2 bidirectional Connect using a resistor divider to VOUT2 to set OVP threshold and VOUT in CV mode for channel-2.
17 ISN2 input Switch current sense negative input (-) for channel-2; connect to GND connection of external sense resistor.
18 ISP2 input Switch current sense positive input (+) for channel-2; connect to external sense resistor between N-channel FET and ground.
19 GATE2 output Channel-2 gate driver output for external N-channel FET (0V to 8.8V).
20 PGND power_in Power ground for high-current return path.
21 VCC power_out 7.5-V low-dropout regulator output providing internal bias voltage.
22 GATE1 output Channel-1 gate driver output for external N-channel FET (0V to 8.8V).
23 ISP1 input Switch current sense positive input (+) for channel-1; connect to external sense resistor between N-channel FET and ground.
24 ISN1 input Switch current sense negative input (-) for channel-1; connect to GND connection of external sense resistor.
25 FB1/OV1 bidirectional Connect using a resistor divider to VOUT1 to set OVP threshold and VOUT in CV mode for channel-1.
26 CSP1 input High-side current sense amplifier positive input (+) for channel-1; accepts 0V to 60V common-mode voltage.
27 CSN1 input High-side current sense amplifier negative input (-) for channel-1.
28 PDRV1 output Channel-1 P-channel gate driver output; connect to gate of external series P-channel FET switch.
29 COMP1 bidirectional Connect to integral or integral-proportional compensation network to ensure stability for channel-1.
30 AGND power_in Analog signal ground providing low-impedance return path for analog circuits.
31 VDD power_out 5-V low-dropout regulator output providing bias to SPI logic circuits.
32 RT input Timing resistor pin; connect resistor to ground to set internal clock frequency from 100kHz to 700kHz.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-32(5x5)
Category LED Drivers
Pins 33

CAD (KiCad official)

  • Symbol: TPS92682QRHBRQ1
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: tps92682qrhbrq1-etched.step / tps92682qrhbrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps92682qrhbrq1.step / tps92682qrhbrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (103 pp, sha256 70502486c25119bb, retrieved 2026-10-06, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF