# TPS923611DRLR

**Texas Instruments** · LED Drivers · SOT-563

TPS923611DRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Supply input pin, with a recommended input voltage range of 2.5 V to 5.5 V. |
| 2 | ADIM | input | Enable, shutdown and PWM-controlled analog dimming input, where the FB voltage is proportional to the input PWM duty cycle. |
| 3 | FB | input | Feedback pin for output current; the sense resistor connects from FB to GND, and the FB/PWM absolute maximum voltage is 5.5 V. |
| 4 | GND | power_in | Ground pin. |
| 5 | VOUT | power_out | Output pin; the recommended output voltage for TPS923611DRLR is 5.5 V to 30 V, with an absolute maximum of 32 V. |
| 6 | SW | power_out | Switch pin connected to the drain of the internal low-side switch FET and the source of the internal high-side switch FET; absolute maximum is 32 V (38 V for transients under 10 ns). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-563 |
| Category | LED Drivers |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage range at terminal VIN | VIN | -0.3 |  | 6 | V |  | 4 |
| Voltage range at terminal SW | SW | -1 |  | 32 | V |  | 4 |
| Voltage range at terminal SW (transient) | SW | -1 |  | 38 | V | transient <10ns | 4 |
| Voltage range at terminal VOUT | VOUT | -0.3 |  | 32 | V |  | 4 |
| Voltage range at terminals FB, PWM | FB, PWM | -0.3 |  | 5.5 | V |  | 4 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Input voltage | VIN | 2.5 |  | 5.5 | V |  | 4 |
| Output voltage (TPS923611DRLR) | VOUT | 5.5 |  | 30 | V | TPS923611DRLR | 4 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 4 |
| VIN input voltage range | VIN | 2.5 |  | 5.5 | V |  | 5 |
| VIN under voltage lockout threshold, rising | VIN_UVLO |  | 2.3 | 2.49 | V | VIN rising | 5 |
| VIN under voltage lockout threshold, falling | VIN_UVLO |  | 2.05 | 2.17 | V | VIN falling | 5 |
| Quiescent current into VIN pin | IQ |  | 260 | 300 | µA | Chip enable. No switching. | 5 |
| Shutdown current into VIN pin | ISD |  | 0.13 | 0.25 | µA | ADIM = 0 (IC disabled), TJ = 25 °C | 5 |
| Shutdown current into VIN pin | ISD |  | 0.13 | 0.5 | µA | ADIM = 0 (IC disabled), TJ up to 85°C | 5 |
| Low-side switch FET on resistance (TPS923610, TPS923611) | RDSON_LS |  | 280 | 400 | mΩ |  | 5 |
| Low-side switch FET on resistance (TPS923610, TPS923611) | RDSON_LS |  | 280 | 300 | mΩ | TJ = 25°C | 5 |
| High-side switch FET on resistance (TPS923610, TPS923611) | RDSON_HS |  | 600 | 900 | mΩ |  | 5 |
| High-side switch FET on resistance (TPS923610, TPS923611) | RDSON_HS |  | 600 | 680 | mΩ | TJ = 25°C | 5 |
| VFB at PWM duty cycle 100% (TPS923610, TPS923611) | VFB | 195 | 200 | 206 | mV | PWM duty cycle 100% (TPS923610, TPS923611) | 5 |
| VFB at PWM duty cycle 100% (TPS923610, TPS923611), TJ = 25°C | VFB | 198 | 200 | 203 | mV | TJ = 25°C | 5 |
| VFB at PWM duty cycle 10% (TPS923610, TPS923611) | VFB | 14.5 | 20.2 | 25.5 | mV | PWM duty cycle 10% (TPS923610, TPS923611) | 5 |
| VFB at PWM duty cycle 10% (TPS923610, TPS923611), TJ = 25°C | VFB | 18 | 20.2 | 22 | mV | TJ = 25°C | 5 |
| VFB at PWM duty cycle 1% (TPS923610, TPS923611) | VFB | 1.7 | 2.2 | 2.7 | mV | PWM duty cycle 1% (TPS923610, TPS923611) TJ = 25°C | 5 |
| FET switching peak current limit (TPS923610, TPS923611) | ILIM | 1.6 | 1.8 | 2.1 | A |  | 6 |
| VOUT over-voltage rising threshold (TPS923611, TPS923612) | VOVP_R | 29.6 | 30.5 | 31.4 | V | TJ up to 85°C | 6 |
| Switching frequency (TPS923610DRLR, TPS923611DRLR, TPS923612DRVR) | FSW |  | 1.1 |  | MHz | TPS923610DRLR, TPS923611DRLR, TPS923612DRVR | 5 |
| FB pin bias current | IFB |  | 0.1 |  | µA | VFB=200mV | 5 |
| Input capacitance, effective value (recommended) | CIN |  | 1 |  | µF |  | 4 |
| Output capacitance, effective value (recommended) | COUT |  | 1 |  | µF |  | 4 |
| ADIM logic high threshold | VADIM_H |  | 1.2 |  | V | TJ up to 85°C | 5 |
| ADIM logic low threshold | VADIM_L |  | 0.385 |  | V | TJ up to 85°C | 5 |
| ADIM pin internal pull down resistor | RADIM_PD |  | 600 |  | kΩ |  | 5 |
| ADIM first pulse high time to enable device | tADIM_EN |  | 40 |  | us |  | 5 |
| ADIM logic low time to shutdown | tADIM_SD |  | 2.5 |  | ms |  | 5 |
| ADIM minimum PWM on time for dimming | tADIM_PWM |  | 20 |  | ns |  | 5 |
| VFB at PWM duty cycle 0.1% (TPS923610, TPS923611) | VFB |  | 0.3 |  | mV | PWM duty cycle 0.1% (TPS923610, TPS923611), TJ = 25°C | 5 |
| Minimum duty cycle of switching operation (TPS923610DRLR, TPS923611DRLR, TPS923612DRVR) | Dmin |  | 15 |  | % |  | 6 |
| VOUT over-voltage falling threshold (hysteresis) | VOVP_HYS |  | 1 |  | V |  | 6 |
| FET switching start-up peak current | ILIM_START |  | 0.8 |  | A |  | 6 |
| Thermal shutdown rising threshold | TTSD_R |  | 170 |  | °C | TJ rising | 6 |
| Thermal shutdown falling threshold | TTSD_F |  | 150 |  | °C | TJ falling | 6 |
| Junction-to-ambient thermal resistance | RθJA |  | 142.7 |  | °C/W | SOT563 DRL, standard | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 72.6 |  | °C/W | SOT563 DRL, standard | 4 |
| Junction-to-board thermal resistance | RθJB |  | 31.6 |  | °C/W | SOT563 DRL, standard | 4 |
| Junction-to-top characterization parameter | ψJT |  | 2.3 |  | °C/W | SOT563 DRL, standard | 4 |
| Junction-to-board characterization parameter | ψJB |  | 30.5 |  | °C/W | SOT563 DRL, standard | 5 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | 1. The output capacitor COUT must be put close to VOUT pin. Having the ground of COUT close to the GND pin (GND copper pour) is also beneficial because there is large ground return current flowing bet | 19 |

## CAD (KiCad official)

- Symbol: `TPS923611DRLR`
- Footprint: `Package_TO_SOT_SMD:SOT-563`
- 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files: `tps923611drlr-etched.step` / `tps923611drlr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps923611drlr.step` / `tps923611drlr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps923611.pdf) (32 pp, sha256 `300165c734761355`, retrieved 2026-10-19, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps923611drlr-datasheet.pdf)