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TPS7B8150QKVURQ1

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Texas Instruments Linear Voltage Regulators (LDO), TO-252-4. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS7B8150QKVURQ1

Texas Instruments · Linear Voltage Regulators (LDO) · TO-252-4

TPS7B8150QKVURQ1 from Texas Instruments, in a TO-252-4. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input supply pin (3 V to 40 V operating, 45 V absolute maximum); use a ceramic capacitor of the recommended value or larger from IN to GND, placed as close to the device as possible.
2 EN input Enable input: drive above VIH (2 V min) to turn the regulator on, below VIL (0.7 V max) to put the LDO in shutdown mode; high-voltage tolerant and can be tied to IN.
3 GND power_in Ground reference.
4 DNC unconnected Do not connect to a bias voltage; connect this pin to ground or leave it floating.
5 OUT power_out Regulated output (150 mA max); requires an output capacitor to GND of 1 µF to 200 µF with ESR of 0.001 Ω to 5 Ω for stability, placed close to the device.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TO-252-4
Category Power Supply Chip
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage (unregulated) VIN -0.3 45 V 45 V withstand for 200 ms 4
Enable input voltage VEN -0.3 V max = VIN 4
Regulated output voltage VOUT -0.3 7 V 4
Junction temperature range TJ -40 150 °C 4
Storage temperature range Tstg -40 150 °C 4
ESD HBM V(ESD) -2000 2000 V AEC Q100-002 4
ESD CDM corner pins V(ESD) -750 750 V AEC Q100-011, corner pins 4
ESD CDM other pins V(ESD) -500 500 V AEC Q100-011, other pins 4
Input voltage VIN 3 40 V 4
Enable input voltage VEN 0 V max = VIN 4
Output capacitor COUT 1 200 µF 4
Output capacitor ESR ESR 0.001 5 Ω f = 10kHz 4
Ambient temperature range TA -40 125 °C 4
Junction temperature range TJ -40 150 °C 4
Junction-to-ambient thermal resistance RθJA 31.1 °C/W KVU (TO-252) 5-pin 5
Junction-to-case (top) thermal resistance RθJC(top) 39.9 °C/W KVU (TO-252) 5-pin 5
Junction-to-board thermal resistance RθJB 9.9 °C/W KVU (TO-252) 5-pin 5
Junction-to-top characterization parameter ψJT 4.2 °C/W KVU (TO-252) 5-pin 5
Junction-to-board characterization parameter ψJB 9.9 °C/W KVU (TO-252) 5-pin 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 2.8 °C/W KVU (TO-252) 5-pin 5
Input voltage VIN 40 V min = VOUT(Nom) + V(Dropout) 5
Shutdown current I(SD) 0.3 1 µA EN = 0V 5
Quiescent current I(Q) 1.9 3.5 µA VIN = 6V to 40V, EN ≥ 2V, IOUT = 0mA 5
Quiescent current I(Q) 2.7 4.5 µA VIN = 6V to 40V, EN ≥ 2V, IOUT = 0.2mA, DRV and KVU packages 5
VIN undervoltage detection V(IN, UVLO) 2.7 V VIN falling until output turns off 5
UVLO hysteresis 200 mV 5
Logic input low level VIL 0.7 V 5
Logic input high level VIH 2 V 5
Enable current IEN 10 nA 5
Regulated output voltage accuracy VOUT -1.5 1.5 % VIN = VOUT + V(Dropout) to 40V, IOUT = 1mA to 150mA 5
Line regulation V(Line-Reg) 10 mV VIN = 6V to 40V, IOUT = 10mA 5
Load regulation V(Load-Reg) 10 mV VIN = 14V, IOUT = 1mA to 150mA, DRV and KVU packages 5
Dropout voltage V(Dropout) 325 585 mV VOUT = 5V, IOUT = 150mA, DRV and KVU packages 5
Dropout voltage V(Dropout) 200 390 mV VOUT = 5V, IOUT = 100mA, DRV and KVU packages 5
Output current IOUT 0 150 mA VOUT in regulation, VIN = 7V (fixed 5V option) 6
Output current limit I(CL) 180 510 690 mA VOUT short to 90% × VOUT 6
Power supply ripple rejection PSRR 60 dB V(Ripple) = 0.5VPP, IOUT = 10mA, frequency = 100Hz, COUT = 2.2µF 6
Junction shutdown temperature T(SD) 175 °C 6
Thermal shutdown hysteresis T(HYST) 20 °C 6

CAD (KiCad official)

  • Symbol: TPS7B8150QKVURQ1
  • Footprint: Package_TO_SOT_SMD:TO-252-4
  • 3D model: TO-252-4 (KiCad packages3D, STEP)
  • 3D model files: tps7b8150qkvurq1-etched.step / tps7b8150qkvurq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7b8150qkvurq1.step / tps7b8150qkvurq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 dd14170409aa766b, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF