# TPS7B6350QPWPRQ1

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-16

TPS7B6350QPWPRQ1 from Texas Instruments, in a HTSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Device input power-supply pin, with a recommended unregulated input range of 4 V to 40 V and an absolute maximum of 45 V. |
| 2 | EN | input | Device enable pin: pull low to disable the device and pull high to enable it; it is a 40-V pin with a recommended range of 0 to VIN. |
| 3 | FSEL | input | Internal oscillator frequency selection pin: low selects the high-frequency oscillator and high selects the low-frequency oscillator; it is a 40-V pin with a recommended range of 0 to VIN. |
| 4 | WTS | input | Watchdog type-selection pin: connect to GND for a window watchdog or pull high for a standard watchdog; it is a 40-V pin with a recommended range of 0 to VIN. |
| 5 | GND | power_in | Ground reference. |
| 6 | NC | unconnected | Not connected; no internal connection. |
| 7 | ROSC | output | Watchdog timer adjustment pin: a resistor between ROSC and GND sets the watchdog monitor duration, and leaving it open or grounding it causes a watchdog fault at WDO; recommended range 0 to 5.5 V. |
| 8 | DELAY | output | Power-good delay period adjustment pin: connect a capacitor to ground to set the power-good delay time; recommended range 0 to 5.5 V. |
| 9 | WD | input | Watchdog service-signal input; recommended range 0 to 5.5 V. |
| 10 | WDO | output | Open-drain watchdog status output: pull up to OUT or a reference voltage through a resistor, and it is pulled low on a watchdog fault; recommended range 0 to 5.5 V. |
| 11 | WD_EN | input | Watchdog enable pin: pull low to enable the watchdog and pull high to disable it; recommended range 0 to 5.5 V. |
| 12 | WRS | input | Window ratio selection pin (window watchdog only): low sets the open:closed window ratio to 1:1 and high sets it to 8:1; recommended range 0 to 5.5 V. |
| 13 | GND | power_in | Ground reference. |
| 14 | PG | output | Open-drain power-good output: pull up to VOUT or a reference through a resistor, and it is pulled low when the output voltage is not ready; recommended range 0 to 5.5 V. |
| 15 | PGADJ | input | Power-good threshold adjustment pin: a resistor divider between PGADJ and OUT sets the threshold, and connecting it to ground sets the threshold to 91.6% of VOUT; recommended range 0 to 5.5 V. |
| 16 | OUT | output | Device 3.3-V or 5-V regulated output voltage pin; recommended output range 0 to 5.5 V with output current of 0 to 300 mA. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-16 |
| Category | Power Management (PMIC) |
| Pins | 17 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Unregulated input IN, EN |  | -0.3 |  | 45 | V |  | 5 |
| Internal oscillator reference voltage ROSC |  | -0.3 |  | 7 | V |  | 5 |
| Power-good delay-timer output DELAY |  | -0.3 |  | 7 | V |  | 5 |
| Regulated output OUT |  | -0.3 |  | 7 | V |  | 5 |
| Power-good output voltage PG |  | -0.3 |  | 7 | V |  | 5 |
| Watchdog status output voltage WDO |  | -0.3 |  | 7 | V |  | 5 |
| Watchdog frequency selection, watchdog-type selection FSEL, WTS |  | -0.3 |  | 45 | V |  | 5 |
| Watchdog enable WD_EN |  | -0.3 |  | 7 | V |  | 5 |
| Watchdog service signal voltage WD |  | -0.3 |  | 7 | V |  | 5 |
| Window ratio selection WRS |  | -0.3 |  | 7 | V |  | 5 |
| Power-good threshold-adjustment voltage PGADJ |  | -0.3 |  | 7 | V |  | 5 |
| Operating junction temperature TJ | TJ | -40 |  | 150 | °C |  | 5 |
| Storage temperature Tstg | Tstg | -65 |  | 150 | °C |  | 5 |
| Unregulated input IN |  | 4 |  | 40 | V |  | 5 |
| 40-V pins EN, FSEL, WTS |  | 0 |  |  | V | Maximum printed as VIN | 5 |
| Regulated output OUT |  | 0 |  | 5.5 | V |  | 5 |
| Power good, watchdog status, reference oscillator PG, WDO, ROSC |  | 0 |  | 5.5 | V |  | 5 |
| Low voltage pins WD, WD_EN, PGADJ, DELAY, WRS |  | 0 |  | 5.5 | V |  | 5 |
| Output current |  | 0 |  | 300 | mA |  | 5 |
| Ambient temperature TA | TA | -40 |  | 125 | °C |  | 5 |
| Input voltage VIN | VIN | 4 |  | 40 | V |  | 6 |
| Input quiescent current, 5-V VOUT, watchdog disabled | IQ |  | 19 | 29.6 | µA | VIN = 5.6 V to 40 V; EN = ON; watchdog disabled; IOUT < 1 mA; TJ < 80°C | 6 |
| Input quiescent current, 5-V VOUT, watchdog enabled, IOUT < 1 mA | IQ |  | 28 | 42 | µA | VIN = 5.6 V to 40 V; EN = ON; watchdog enabled; IOUT < 1 mA | 6 |
| Input quiescent current, 5-V VOUT, watchdog enabled, IOUT < 100 mA | IQ |  | 78 | 98 | µA | VIN = 5.6 V to 40 V; EN = ON; watchdog enabled; IOUT < 100 mA | 6 |
| Regulated output VOUT (±2 %) | VOUT | -2 |  | 2 | % | VIN = 5.6 V to 40 V (fixed 5-V VOUT); IOUT = 0 to 300 mA; -40°C ≤ TJ ≤ 125°C | 6 |
| Regulated output VOUT (±2.5 %) | VOUT | -2.5 |  | 2.5 | % | VIN = 5.6 V to 40 V (fixed 5-V VOUT); IOUT = 0 to 300 mA | 6 |
| Dropout voltage (VIN, VOUT) at 300 mA | V(dropout) |  | 300 | 400 | mV | IOUT = 300 mA | 7 |
| Dropout voltage (VIN, VOUT) at 200 mA | V(dropout) |  | 170 | 325 | mV | IOUT = 200 mA | 7 |
| Output current | IOUT | 0 |  | 300 | mA | VOUT in regulation | 7 |
| Output current limit | I(LIM) | 301 | 680 | 1000 | mA | VOUT shorted to ground, VIN = 5.6 V to 40 V | 7 |
| Default power-good threshold | V(PG_TH) | 89.6 | 91.6 | 93.6 | % of VOUT | VOUT powered above the internally set tolerance; PGADJ pin shorted to ground | 7 |
| Switching voltage for the power-good adjust pin | V(PGADJ_TH) | 1.067 | 1.1 | 1.133 | V | VOUT is falling | 7 |
| DELAY capacitor charging current | I(DLY_CHG) | 3 | 5 | 10 | µA |  | 7 |
| DELAY pin threshold to release PG high | V(DLY_TH) | 0.95 | 1 | 1.05 | V | Voltage at DELAY pin is ramped up | 7 |
| Voltage reference (ROSC) | VROSC | 0.95 | 1 | 1.05 | V |  | 7 |
| Pulldown current for the WD pin | IWD |  | 2 | 4 | µA | VWDO = 5 V | 7 |
| Power-good deglitch time | t(DEGLITCH) | 50 | 180 | 250 | µs |  | 9 |
| Fixed power-good delay | t(DLY_FIX) |  | 248 | 900 | µs | No capacitor connect at DELAY pin | 9 |
| Watchdog window duration, FSEL low | t(WD) | 9 | 10 | 11 | ms | R(ROSC) = 20 kΩ ±1%, FSEL = LOW | 9 |
| Watchdog window duration, FSEL high | t(WD) | 45 | 50 | 55 | ms | R(ROSC) = 20 kΩ ±1%, FSEL = HIGH | 9 |
| Tolerance of watchdog window duration using external resistor | t(WD_TOL) | -10 |  | 10 | % | Excludes tolerance of R(ROSC) = 20 kΩ to 100 kΩ | 9 |
| Watchdog output resetting time, FSEL low | t(WD_RESET) | 1.8 | 2 | 2.2 | ms | R(ROSC) = 20 kΩ ± 1%, FSEL = LOW | 9 |
| Watchdog output resetting time, FSEL high | t(WD_RESET) | 9 | 10 | 11 | ms | R(ROSC) = 20 kΩ ± 1%, FSEL = HIGH | 9 |
| Junction-to-ambient thermal resistance RθJA | RθJA |  | 39.7 |  | °C/W |  | 6 |
| Junction-to-case (top) thermal resistance RθJC(top) | RθJC(top) |  | 28.9 |  | °C/W |  | 6 |
| Junction-to-board thermal resistance RθJB | RθJB |  | 23.8 |  | °C/W |  | 6 |
| Junction-to-case (bottom) thermal resistance RθJC(bot) | RθJC(bot) |  | 3.1 |  | °C/W |  | 6 |
| Input sleep current | I(SLEEP) |  | 4 |  | µA | EN = OFF | 6 |
| Undervoltage lockout, falling | V(UVLO) |  | 2.6 |  | V | Ramp VIN down until output is turned off | 6 |
| Low-level input voltage (EN, WTS, FSEL) | VIL |  | 0.7 |  | V |  | 6 |
| High-level input voltage (EN, WTS, FSEL) | VIH |  | 2 |  | V |  | 6 |
| Low-level input threshold voltage for watchdog enable pin | VIL |  | 0.7 |  | V | Watchdog enabled | 6 |
| High-level input threshold voltage for watchdog enable pin | VIH |  | 2 |  | V | Watchdog disabled | 6 |
| Low-level watchdog output voltage (WDO) | VOL |  | 0.4 |  | V | IWDO = 5 mA | 7 |
| PG output, low voltage | VOL(PG) |  | 0.4 |  | V | IOL = 5 mA, PG pulled low | 7 |
| Power-good hysteresis | V(PG_HYST) |  | 2 |  | % of VOUT | VOUT falling below the internally set tolerance hysteresis | 7 |
| Line regulation | ΔVOUT(ΔVIN) |  | 10 |  | mV | VIN = 5.6 V to 40 V | 7 |
| Load regulation | ΔVOUT(ΔIOUT) |  | 20 |  | mV | IOUT = 1 mA to 300 mA | 7 |
| Junction shutdown temperature | T(SD) |  | 175 |  | °C |  | 7 |
| Power-supply ripple rejection at 100 Hz | PSRR |  | 60 |  | dB | IOUT = 100 mA; COUT = 10 µF; f = 100 Hz | 7 |

## CAD (KiCad official)

- Symbol: `TPS7B6350QPWPRQ1`
- Footprint: `Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm`
- 3D model: HTSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `tps7b6350qpwprq1-etched.step` / `tps7b6350qpwprq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7b6350qpwprq1.step` / `tps7b6350qpwprq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps7b63-q1) (34 pp, sha256 `6e0f7f9b9769fe0e`, retrieved 2026-10-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps7b6350qpwprq1-datasheet.pdf)