component
TPS7B6333QPWPRQ1
Public Made by Adomby adom
Texas Instruments Pre-ordered Chips, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTPS7B6333QPWPRQ1
Texas Instruments · Pre-ordered Chips · HTSSOP-16-EP
TPS7B6333QPWPRQ1 from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Device input power-supply pin, operating range 4 V to 40 V. |
| 2 | EN | input | Device enable pin: pull low to disable the device, pull high to enable it. |
| 3 | FSEL | input | Internal oscillator frequency selection: low selects the high-frequency oscillator, high selects the low-frequency oscillator. |
| 4 | WTS | input | Watchdog type selection: connect to GND for window watchdog, pull high for standard watchdog. |
| 5 | GND | power_in | Ground reference. |
| 6 | NC | unconnected | No internal connection. |
| 7 | ROSC | output | Watchdog timer adjustment: connect a resistor to GND to set the watchdog monitor duration; open or grounded causes a watchdog fault at WDO. |
| 8 | DELAY | output | Power-good delay adjustment: connect a capacitor to ground to set the power-good delay time. |
| 9 | WD | input | Watchdog service-signal input pin. |
| 10 | WDO | output | Open-drain watchdog status output, pull up to OUT or a reference through a resistor; pulled low on a watchdog fault. |
| 11 | WD_EN | input | Watchdog enable pin: pull low to enable the watchdog, pull high to disable it. |
| 12 | WRS | input | Window ratio selection (window watchdog only): low sets open:closed ratio 1:1, high sets 8:1. |
| 13 | GND | power_in | Ground reference. |
| 14 | PG | output | Open-drain power-good output, pull up to VOUT or a reference through a resistor; pulled to ground when the output voltage is not ready. |
| 15 | PGADJ | input | Power-good threshold adjustment: use a resistor divider between PGADJ and OUT, or connect to ground for a threshold of 91.6% of VOUT. |
| 16 | OUT | power_out | Regulated 3.3-V output voltage pin for this device (TPS7B6333), up to 300 mA. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-16-EP |
| Category | Interface ICs |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Unregulated input IN, EN | -0.3 | 45 | V | 5 | |||
| ROSC voltage | -0.3 | 7 | V | 5 | |||
| Regulated output OUT | -0.3 | 7 | V | 5 | |||
| FSEL, WTS voltage | -0.3 | 45 | V | 5 | |||
| WD_EN voltage | -0.3 | 7 | V | 5 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | HBM per AEC Q100-002 | 5 | |
| ESD CDM all pins | V(ESD) | -500 | 500 | V | CDM per AEC Q100-011, all pins | 5 | |
| Input voltage IN | VIN | 4 | 40 | V | 5 | ||
| Output OUT | 0 | 5.5 | V | 5 | |||
| Output current | IOUT | 0 | 300 | mA | 5 | ||
| Ambient temperature | TA | -40 | 125 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 39.7 | °C/W | PWP (HTSSOP) 16 pins | 6 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 28.9 | °C/W | 6 | |||
| Junction-to-board thermal resistance | RθJB | 23.8 | °C/W | 6 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 3.1 | °C/W | 6 | |||
| Input voltage | VIN | 4 | 40 | V | 6 | ||
| Input sleep current | I(SLEEP) | 4 | µA | EN = OFF | 6 | ||
| Input quiescent current, watchdog disabled | I(Q) | 19 | 29.6 | µA | VIN = 4 V to 40 V for fixed 3.3-V VOUT; EN = ON; watchdog disabled; IOUT < 1 mA; TJ < 80°C | 6 | |
| Input quiescent current, watchdog enabled | I(Q) | 28 | 42 | µA | VIN = 4 V to 40 V for fixed 3.3-V VOUT; EN = ON; watchdog enabled; IOUT < 1 mA | 6 | |
| Input quiescent current, IOUT < 100 mA | I(Q) | 78 | 98 | µA | VIN = 4 V to 40 V for fixed 3.3-V VOUT; EN = ON; watchdog enabled; IOUT < 100 mA | 6 | |
| Undervoltage lockout, falling | V(UVLO) | 2.6 | V | Ramp VIN down until output is turned off | 6 | ||
| UVLO hysteresis | V(UVLO_HYST) | 0.5 | V | 6 | |||
| Low-level input voltage (EN, WTS, FSEL) | VIL | 0.7 | V | 6 | |||
| High-level input voltage (EN, WTS, FSEL) | VIH | 2 | V | 6 | |||
| Hysteresis (EN, WTS, FSEL) | Vhys | 150 | mV | 6 | |||
| WD_EN low-level input threshold | VIL | 0.7 | V | Watchdog enabled | 6 | ||
| WD_EN high-level input threshold | VIH | 2 | V | Watchdog disabled | 6 | ||
| WD_EN pulldown current | IWD_EN | 3 | µA | VWD_EN = 5 V | 6 | ||
| Regulated output, TJ -40 to 125°C | VOUT | -2 | 2 | % | VIN = 4 V to 40 V for fixed 3.3-V VOUT, IOUT = 0 to 300 mA, -40°C ≤ TJ ≤ 125°C | 6 | |
| Regulated output | VOUT | -2.5 | 2.5 | % | VIN = 4 V to 40 V for fixed 3.3-V VOUT; IOUT = 0 to 300 mA | 6 | |
| Line regulation | ΔVOUT(ΔVIN) | 10 | mV | VIN = 5.6 V to 40 V | 7 | ||
| Load regulation | ΔVOUT(ΔIOUT) | 20 | mV | IOUT = 1 mA to 300 mA | 7 | ||
| Dropout voltage | V(dropout) | 300 | 400 | mV | IOUT = 300 mA | 7 | |
| Dropout voltage | V(dropout) | 170 | 325 | mV | IOUT = 200 mA | 7 | |
| Output current | IOUT | 0 | 300 | mA | VOUT in regulation | 7 | |
| Output current limit | I(LIM) | 301 | 680 | 1000 | mA | VOUT shorted to ground, VIN = 5.6 V to 40 V | 7 |
| PSRR | PSRR | 60 | dB | IOUT = 100 mA; COUT = 10 µF; f = 100 Hz | 7 | ||
| PSRR | PSRR | 40 | dB | IOUT = 100 mA; COUT = 10 µF; f = 100 kHz | 7 | ||
| PG output, low voltage | VOL(PG) | 0.4 | V | IOL = 5 mA, PG pulled low | 7 | ||
| PG pin leakage current | Ilkg(PG) | 1 | µA | PG pulled to VOUT through a 10-kΩ resistor | 7 | ||
| Default power-good threshold | V(PG_TH) | 89.6 | 91.6 | 93.6 | % of VOUT | VOUT powered above the internally set tolerance, PGADJ pin shorted to ground | 7 |
| Power-good hysteresis | V(PG_HYST) | 2 | % of VOUT | VOUT falling below the internally set tolerance hysteresis | 7 | ||
| PGADJ switching voltage | V(PGADJ_TH) | 1.067 | 1.1 | 1.133 | V | VOUT is falling | 7 |
| DELAY capacitor charging current | I(DLY_CHG) | 3 | 5 | 10 | µA | 7 | |
| DELAY pin threshold to release PG high | V(DLY_TH) | 0.95 | 1 | 1.05 | V | Voltage at DELAY pin is ramped up | 7 |
| DELAY capacitor discharging current | I(DLY_DIS) | 0.5 | mA | VDELAY = 1 V | 7 | ||
| ROSC voltage reference | VROSC | 0.95 | 1 | 1.05 | V | 7 | |
| Watchdog low-level threshold (WD, WRS) | VIL | 30 | % of VOUT | For WD and WRS pins | 7 | ||
| Watchdog high-level threshold (WD, WRS) | VIH | 70 | % of VOUT | For WD and WRS pins | 7 | ||
| Watchdog hysteresis | V(HYST) | 10 | % of VOUT | 7 | |||
| WD pin pulldown current | IWD | 2 | 4 | µA | VWDO = 5 V | 7 | |
| Low-level watchdog output | VOL | 0.4 | V | IWDO = 5 mA | 7 | ||
| WDO pin leakage current | Ilkg | 1 | µA | WDO pin pulled to VOUT through 10-kΩ resistor | 7 | ||
| Junction temperature | TJ | -40 | 150 | °C | 7 | ||
| Junction shutdown temperature | T(SD) | 175 | °C | 7 | |||
| Hysteresis of thermal shutdown | T(HYST) | 25 | °C | 8 | |||
| Power-good deglitch time | t(DEGLITCH) | 50 | 180 | 250 | µs | 9 | |
| Fixed power-good delay | t(DLY_FIX) | 248 | 900 | µs | No capacitor connect at DELAY pin | 9 | |
| Watchdog window duration, FSEL low | t(WD) | 9 | 10 | 11 | ms | R(ROSC) = 20 kΩ ±1%, FSEL = LOW | 9 |
| Watchdog window duration, FSEL high | t(WD) | 45 | 50 | 55 | ms | R(ROSC) = 20 kΩ ±1%, FSEL = HIGH | 9 |
| Tolerance of watchdog window duration | t(WD_TOL) | -10 | 10 | % | Excludes tolerance of R(ROSC) = 20 kΩ to 100 kΩ | 9 | |
| Watchdog service-signal duration | tp(WD) | 100 | µs | 9 | |||
| Watchdog output resetting time, FSEL low | t(WD_RESET) | 1.8 | 2 | 2.2 | ms | R(ROSC) = 20 kΩ ± 1%, FSEL = LOW | 9 |
| Watchdog output resetting time, FSEL high | t(WD_RESET) | 9 | 10 | 11 | ms | R(ROSC) = 20 kΩ ± 1%, FSEL = HIGH | 9 |
CAD (KiCad official)
- Symbol:
TPS7B6333QPWPRQ1 - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files:
tps7b6333qpwprq1-etched.step/tps7b6333qpwprq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7b6333qpwprq1.step/tps7b6333qpwprq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (34 pp, sha256
6e0f7f9b9769fe0e, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).