component
TPS7B4253QPWPRQ1
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS7B4253QPWPRQ1
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20-EP
TPS7B4253QPWPRQ1 from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Regulated output that needs a capacitor of 10 µF to 500 µF with ESR of 0.001 Ω to 20 Ω when FB is tied to OUT, placed close to the device pins and referenced to GND. |
| 2 | NC | unconnected | No internal connection. |
| 3 | NC | unconnected | No internal connection. |
| 4 | NC | unconnected | No internal connection. |
| 5 | NC | unconnected | No internal connection. |
| 6 | GND | power_in | Ground reference for the device. |
| 7 | NC | unconnected | No internal connection. |
| 8 | NC | unconnected | No internal connection. |
| 9 | NC | unconnected | No internal connection. |
| 10 | FB | input | Feedback pin that can be connected to an external resistor divider to select the output voltage; the datasheet recommends R1 and R2 between 10 kΩ and 100 kΩ. |
| 11 | ADJ | input | Connects the reference voltage (1.5 V to 18 V for HTSSOP); the reference can be applied directly or through a divider for a lower output voltage, and a capacitor should be placed near the pin to compensate line effects. |
| 12 | NC | unconnected | No internal connection. |
| 13 | NC | unconnected | No internal connection. |
| 14 | NC | unconnected | No internal connection. |
| 15 | GND | power_in | Ground reference for the device. |
| 16 | NC | unconnected | No internal connection. |
| 17 | NC | unconnected | No internal connection. |
| 18 | NC | unconnected | No internal connection. |
| 19 | EN | input | Enable pin; when it is below the threshold the device enters standby, with a rising threshold of 2 V (max) and a falling threshold of 0.7 V (min), and the pin is rated 0 V to 40 V. |
| 20 | IN | input | Device power input with a recommended operating range of 4 V to 40 V (absolute maximum -40 V to 45 V); place a capacitor close to the device pins to compensate line effects. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage, non-regulated (IN) | -40 | 45 | V | 4 | |||
| Enable input voltage (EN) | -40 | 45 | V | 4 | |||
| Regulated output voltage (OUT) | -1 | 45 | V | 4 | |||
| Input-to-output voltage difference | IN, OUT | -40 | 45 | V | 4 | ||
| Reference voltage (ADJ) | -0.3 | 45 | V | 4 | |||
| Tracker feedback input voltage (FB) | -1 | 45 | V | 4 | |||
| Reference voltage minus input voltage | ADJ − IN | 18 | V | 4 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| HBM ESD, NC pins | V(ESD) | -2000 | 2000 | kV | NC pins, AEC Q100-002 | 4 | |
| HBM ESD, all pins except NC | V(ESD) | -4000 | 4000 | kV | All pins except NC, AEC Q100-002 | 4 | |
| CDM ESD | V(ESD) | -1000 | 1000 | kV | AEC Q100-011 | 4 | |
| Non-regulated input voltage (IN) | VIN | 4 | 40 | V | 4 | ||
| Enable input voltage | VEN | 0 | 40 | V | 4 | ||
| Adjust input voltage (HTSSOP) | VADJ | 1.5 | 18 | V | HTSSOP package | 4 | |
| Tracker feedback input voltage (HTSSOP) | VFB | 1.5 | 18 | V | HTSSOP package | 4 | |
| Output voltage (HTSSOP) | VOUT | 1.5 | 40 | V | HTSSOP package | 4 | |
| Output capacitor requirement | C(OUT) | 10 | 500 | µF | 4 | ||
| Output ESR requirement | 0.001 | 20 | Ω | f = 10kHz | 4 | ||
| Operating junction temperature range | TJ | -40 | 150 | °C | 4 | ||
| Junction-to-ambient thermal resistance (PWP, 20 pin) | RθJA | 45.9 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance (PWP, 20 pin) | RθJC(top) | 29.2 | °C/W | 5 | |||
| Junction-to-board thermal resistance (PWP, 20 pin) | RθJB | 24.7 | °C/W | 5 | |||
| Junction-to-top characterization parameter (PWP, 20 pin) | ψJT | 1.3 | °C/W | 5 | |||
| Junction-to-board characterization parameter (PWP, 20 pin) | ψJB | 24.5 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance (PWP, 20 pin) | RθJC(bot) | 3.7 | °C/W | 5 | |||
| Output voltage tracking accuracy | ΔVO | -4 | 4 | mV | IOUT = 100µA to 300mA, VIN = 4 to 40V, VADJ < VIN − 1V, 1.5V < VADJ < 18V (HTSSOP) | 5 | |
| Dropout voltage | V(DROPOUT) | 320 | 520 | mV | IOUT = 200mA, VIN = VADJ ≥ 4V | 5 | |
| Output current limit | IO(lim) | 301 | 450 | 520 | mA | VADJ = 5V, OUT short to GND | 5 |
| Reverse current, IN | IR(IN) | -2 | 0 | µA | VIN = 0V, VOUT = 40V, VADJ = 5V | 5 | |
| Reverse current, IN negative | IR(-IN) | -10 | 0 | µA | VIN = -40V, VOUT = 0V, VADJ = 5V | 5 | |
| Quiescent current | IQ | 2 | 4 | µA | 4V ≤ VIN ≤ 40V, VADJ = 0V; VEN = 0V | 5 | |
| Quiescent current | IQ | 7 | 18 | µA | 4V ≤ VIN ≤ 40V, VEN ≥ 2V, VADJ < 0.8V | 5 | |
| Quiescent current | IQ | 60 | 100 | µA | 4V ≤ VIN ≤ 40V, IOUT < 100µA, VADJ = 5V | 5 | |
| Quiescent current | IQ | 350 | 400 | µA | 4V ≤ VIN ≤ 40V, IOUT < 300mA, VADJ = 5V | 5 | |
| Quiescent current in dropout region | IQ(DROPOUT) | 70 | 140 | µA | VIN = VADJ = 5V, IOUT = 100µA | 5 | |
| Adjust low-level signal threshold (HTSSOP) | V(ADJ_LOW) | 0 | 0.8 | V | VOUT = 0V | 5 | |
| Adjust high-level signal threshold (HTSSOP) | V(ADJ_HIGH) | 1.5 | 18 | V | /VOUT − VADJ/ < 4mV | 5 | |
| Enable low-level signal threshold | V(EN_LOW) | 0 | 0.7 | V | VOUT = 0V | 5 | |
| Enable high-level signal threshold | V(EN_HIGH) | 2 | 40 | V | OUT stable | 6 |
CAD (KiCad official)
- Symbol:
TPS7B4253QPWPRQ1 - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps7b4253qpwprq1-etched.step/tps7b4253qpwprq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7b4253qpwprq1.step/tps7b4253qpwprq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (41 pp, sha256
a41e03c9d45f34b8, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS7B4253QPWPRQ1
**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20-EP
TPS7B4253QPWPRQ1 from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Regulated output that needs a capacitor of 10 µF to 500 µF with ESR of 0.001 Ω to 20 Ω when FB is tied to OUT, placed close to the device pins and referenced to GND. |
| 2 | NC | unconnected | No internal connection. |
| 3 | NC | unconnected | No internal connection. |
| 4 | NC | unconnected | No internal connection. |
| 5 | NC | unconnected | No internal connection. |
| 6 | GND | power_in | Ground reference for the device. |
| 7 | NC | unconnected | No internal connection. |
| 8 | NC | unconnected | No internal connection. |
| 9 | NC | unconnected | No internal connection. |
| 10 | FB | input | Feedback pin that can be connected to an external resistor divider to select the output voltage; the datasheet recommends R1 and R2 between 10 kΩ and 100 kΩ. |
| 11 | ADJ | input | Connects the reference voltage (1.5 V to 18 V for HTSSOP); the reference can be applied directly or through a divider for a lower output voltage, and a capacitor should be placed near the pin to compensate line effects. |
| 12 | NC | unconnected | No internal connection. |
| 13 | NC | unconnected | No internal connection. |
| 14 | NC | unconnected | No internal connection. |
| 15 | GND | power_in | Ground reference for the device. |
| 16 | NC | unconnected | No internal connection. |
| 17 | NC | unconnected | No internal connection. |
| 18 | NC | unconnected | No internal connection. |
| 19 | EN | input | Enable pin; when it is below the threshold the device enters standby, with a rising threshold of 2 V (max) and a falling threshold of 0.7 V (min), and the pin is rated 0 V to 40 V. |
| 20 | IN | input | Device power input with a recommended operating range of 4 V to 40 V (absolute maximum -40 V to 45 V); place a capacitor close to the device pins to compensate line effects. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage, non-regulated (IN) | | -40 | | 45 | V | | 4 |
| Enable input voltage (EN) | | -40 | | 45 | V | | 4 |
| Regulated output voltage (OUT) | | -1 | | 45 | V | | 4 |
| Input-to-output voltage difference | IN, OUT | -40 | | 45 | V | | 4 |
| Reference voltage (ADJ) | | -0.3 | | 45 | V | | 4 |
| Tracker feedback input voltage (FB) | | -1 | | 45 | V | | 4 |
| Reference voltage minus input voltage | ADJ − IN | | | 18 | V | | 4 |
| Operating junction temperature | TJ | -40 | | 150 | °C | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| HBM ESD, NC pins | V(ESD) | -2000 | | 2000 | kV | NC pins, AEC Q100-002 | 4 |
| HBM ESD, all pins except NC | V(ESD) | -4000 | | 4000 | kV | All pins except NC, AEC Q100-002 | 4 |
| CDM ESD | V(ESD) | -1000 | | 1000 | kV | AEC Q100-011 | 4 |
| Non-regulated input voltage (IN) | VIN | 4 | | 40 | V | | 4 |
| Enable input voltage | VEN | 0 | | 40 | V | | 4 |
| Adjust input voltage (HTSSOP) | VADJ | 1.5 | | 18 | V | HTSSOP package | 4 |
| Tracker feedback input voltage (HTSSOP) | VFB | 1.5 | | 18 | V | HTSSOP package | 4 |
| Output voltage (HTSSOP) | VOUT | 1.5 | | 40 | V | HTSSOP package | 4 |
| Output capacitor requirement | C(OUT) | 10 | | 500 | µF | | 4 |
| Output ESR requirement | | 0.001 | | 20 | Ω | f = 10kHz | 4 |
| Operating junction temperature range | TJ | -40 | | 150 | °C | | 4 |
| Junction-to-ambient thermal resistance (PWP, 20 pin) | RθJA | | 45.9 | | °C/W | | 5 |
| Junction-to-case (top) thermal resistance (PWP, 20 pin) | RθJC(top) | | 29.2 | | °C/W | | 5 |
| Junction-to-board thermal resistance (PWP, 20 pin) | RθJB | | 24.7 | | °C/W | | 5 |
| Junction-to-top characterization parameter (PWP, 20 pin) | ψJT | | 1.3 | | °C/W | | 5 |
| Junction-to-board characterization parameter (PWP, 20 pin) | ψJB | | 24.5 | | °C/W | | 5 |
| Junction-to-case (bottom) thermal resistance (PWP, 20 pin) | RθJC(bot) | | 3.7 | | °C/W | | 5 |
| Output voltage tracking accuracy | ΔVO | -4 | | 4 | mV | IOUT = 100µA to 300mA, VIN = 4 to 40V, VADJ < VIN − 1V, 1.5V < VADJ < 18V (HTSSOP) | 5 |
| Dropout voltage | V(DROPOUT) | | 320 | 520 | mV | IOUT = 200mA, VIN = VADJ ≥ 4V | 5 |
| Output current limit | IO(lim) | 301 | 450 | 520 | mA | VADJ = 5V, OUT short to GND | 5 |
| Reverse current, IN | IR(IN) | -2 | | 0 | µA | VIN = 0V, VOUT = 40V, VADJ = 5V | 5 |
| Reverse current, IN negative | IR(-IN) | -10 | | 0 | µA | VIN = -40V, VOUT = 0V, VADJ = 5V | 5 |
| Quiescent current | IQ | | 2 | 4 | µA | 4V ≤ VIN ≤ 40V, VADJ = 0V; VEN = 0V | 5 |
| Quiescent current | IQ | | 7 | 18 | µA | 4V ≤ VIN ≤ 40V, VEN ≥ 2V, VADJ < 0.8V | 5 |
| Quiescent current | IQ | | 60 | 100 | µA | 4V ≤ VIN ≤ 40V, IOUT < 100µA, VADJ = 5V | 5 |
| Quiescent current | IQ | | 350 | 400 | µA | 4V ≤ VIN ≤ 40V, IOUT < 300mA, VADJ = 5V | 5 |
| Quiescent current in dropout region | IQ(DROPOUT) | | 70 | 140 | µA | VIN = VADJ = 5V, IOUT = 100µA | 5 |
| Adjust low-level signal threshold (HTSSOP) | V(ADJ_LOW) | 0 | | 0.8 | V | VOUT = 0V | 5 |
| Adjust high-level signal threshold (HTSSOP) | V(ADJ_HIGH) | 1.5 | | 18 | V | /VOUT − VADJ/ < 4mV | 5 |
| Enable low-level signal threshold | V(EN_LOW) | 0 | | 0.7 | V | VOUT = 0V | 5 |
| Enable high-level signal threshold | V(EN_HIGH) | 2 | | 40 | V | OUT stable | 6 |
## CAD (KiCad official)
- Symbol: `TPS7B4253QPWPRQ1`
- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`
- 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tps7b4253qpwprq1-etched.step` / `tps7b4253qpwprq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7b4253qpwprq1.step` / `tps7b4253qpwprq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps7b4253-q1) (41 pp, sha256 `a41e03c9d45f34b8`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps7b4253qpwprq1-datasheet.pdf)