component
TPS7A9201DSKT
Public Made by Adomby adom
Texas Instruments Pre-ordered Chips, SON-10-EP(2.5x2.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownTPS7A9201DSKT
Texas Instruments · Pre-ordered Chips · SON-10-EP(2.5x2.5)
TPS7A9201DSKT from Texas Instruments, in a SON-10-EP(2.5x2.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output; a 22 µF or greater capacitor must be connected from this pin to GND for stability. |
| 2 | OUT | power_out | Regulated output; a 22 µF or greater capacitor must be connected from this pin to GND for stability. |
| 3 | FB | input | Feedback pin, input to the control loop error amplifier used to set the output voltage of the device. |
| 4 | GND | power_in | Device ground; connect to the device thermal pad. |
| 5 | PG | output | Open-drain power-good indicator for the LDO output voltage; requires a 10-kΩ to 100-kΩ external pullup resistor and can be left floating or connected to GND if not used. |
| 6 | SS_CTRL | input | Soft-start control pin; connect to GND or IN to change the NR/SS capacitor charging current, and connect to GND if no CNR/SS capacitor is used to avoid output overshoot. |
| 7 | EN | input | Enable pin that turns the LDO on if VEN ≥ VIH(EN) and off if VEN ≤ VIL(EN); must be connected to IN if the enable function is not used. |
| 8 | NR/SS | passive | Noise reduction pin; connect an external capacitor to bypass internal bandgap reference noise and to set the output ramp rate to limit inrush current. |
| 9 | IN | power_in | Input supply pin (1.4 V to 6.5 V); a 10 µF or greater input capacitor is required. |
| 10 | IN | power_in | Input supply pin (1.4 V to 6.5 V); a 10 µF or greater input capacitor is required. |
| 11 | Thermal Pad | passive | Connect the thermal pad to the PCB ground plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SON-10-EP(2.5x2.5) |
| Category | Interface ICs |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply voltage range | VIN | 1.4 | 6.5 | V | 4 | ||
| Input supply UVLO | VUVLO | 1.31 | 1.39 | V | VIN rising | 4 | |
| Output voltage accuracy | VOUT | -1 | 1 | % | 0.8 V ≤ VOUT ≤ 5 V, 5 mA ≤ IOUT ≤ 2 A | 4 | |
| Dropout voltage | VDO | 400 | mV | VIN ≥ 1.4 V, 0.8 V ≤ VOUT ≤ 5.0 V, IOUT = 2 A, VFB = 0.8 V, 3% | 4 | ||
| Output current limit | ILIM | 2.3 | 2.6 | 2.9 | A | VOUT forced at 0.9 × VOUT(TARGET), VIN = VOUT(TARGET) + 300 mV | 5 |
| GND pin current | IGND | 2.1 | 3.5 | mA | Both channels enabled, per channel, VIN = 6.5 V, IOUT = 5 mA | 5 | |
| Shutdown GND pin current | ISDN | 0.1 | 15 | µA | Both channels shutdown, per channel, PGx = (open), VIN = 6.5 V, VEN = 0.5 V | 5 | |
| EN pin current | IEN | -0.2 | 0.2 | µA | VIN = 6.5 V, 0 V ≤ VEN ≤ 6.5 V | 5 | |
| EN pin low-level input voltage | VIL(EN) | 0 | 0.4 | V | device disabled | 5 | |
| EN pin high-level input voltage | VIH(EN) | 1.1 | 6.5 | V | device enabled | 5 | |
| SS_CTRL pin current | ISS_CTRL | -0.2 | 0.2 | µA | VIN = 6.5 V, 0 V ≤ VSS_CTRL ≤ 6.5 V | 5 | |
| PG pin threshold | VIT(PG) | 82 | 88.9 | 93 | % | For PG transitioning low with falling VOUT, expressed as a percentage of VOUT(TARGET) | 5 |
| PG pin low-level output voltage | VOL(PG) | 0.4 | V | VOUT < VIT(PG), IPG = -1 mA (current into device) | 5 | ||
| PG pin leakage current | Ilkg(PG) | 1 | µA | VOUT > VIT(PG), VPG = 6.5 V | 5 | ||
| NR/SS pin charging current | INR/SS | 4 | 6.2 | 9 | µA | VNR/SS = GND, 1.4 V ≤ VIN ≤ 6.5 V, VSS_CTRL = GND | 5 |
| NR/SS pin charging current | INR/SS | 65 | 100 | 150 | µA | VNR/SS = GND, 1.4 V ≤ VIN ≤ 6.5 V, VSS_CTRL = VIN | 5 |
| FB pin leakage current | IFB | -100 | 100 | nA | VIN = 6.5 V, VFB = 0.8 V | 5 | |
| Output voltage range | VOUT | 0.8 | 5.2 | V | 0.8, 1.0% to 5.2 + 1.0% | 4 | |
| Reference voltage | VREF | 0.8 | V | 4 | |||
| Output current | IOUT | 0 | 2 | A | 4 | ||
| Power-good pullup resistance | RPG | 10 | 100 | kΩ | 4 | ||
| Junction temperature range | TJ | -40 | 125 | °C | 4 | ||
| Voltage IN, PG, EN | -0.3 | 7 | V | 3 | |||
| Voltage IN, PG, EN pulse | -0.3 | 7.5 | V | 5% duty cycle, pulse duration = 200 µs | 3 | ||
| Voltage NR/SS, FB | -0.3 | 3.6 | V | 3 | |||
| PG sink current | 5 | mA | sink current into device | 3 | |||
| Operating junction temperature | TJ | -55 | 150 | °C | 3 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 3 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | HBM per ANSI/ESDA/JEDEC JS-001 | 4 | |
| ESD CDM | V(ESD) | -500 | 500 | V | CDM per JESD22-C101 | 4 | |
| Junction-to-ambient thermal resistance | RθJA | 56.9 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 46.3 | °C/W | 4 | |||
| Junction-to-board thermal resistance | RθJB | 29.1 | °C/W | 4 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 3.2 | °C/W | 4 | |||
| Line regulation | ΔVOUT(ΔVIN) | 0.003 | %/V | IOUT= 5 mA, 1.4 V ≤ VIN ≤ 6.5 V | 4 | ||
| Load regulation | ΔVOUT(ΔIOUT) | 0.03 | %/A | 5 mA ≤ IOUT ≤ 2 A | 4 | ||
| Output noise voltage | Vn | 4.6 | μVRMS | BW = 10 Hz to 100 kHz, VIN = 1.8 V, VOUT = 0.8 V, IOUT = 2.0 A, CNR/SS = 10 nF, CFF = 10 nF | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | input and output capacitors, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit co | 22 |
CAD (KiCad official)
- Symbol:
TPS7A9201DSKT - Footprint:
Package_SON:WSON-10-1EP_2.5x2.5mm_P0.5mm_EP1.2x2mm - 3D model: SON-10-EP(2.5x2.5) (KiCad packages3D, STEP)
- 3D model files:
tps7a9201dskt-etched.step/tps7a9201dskt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a9201dskt.step/tps7a9201dskt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (35 pp, sha256
3ae79b98655c8256, retrieved 2026-10-23, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).