component
TPS7A9001DSKT
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-10-EP(2.5x2.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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TPS7A9001DSKT
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-10-EP(2.5x2.5)
TPS7A9001DSKT from Texas Instruments, in a WSON-10-EP(2.5x2.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output; a 10 µF or larger capacitor must be connected between this pin and GND for stability, and the output is adjustable from 0.8 V to 5.7 V. |
| 2 | OUT | power_out | Regulated output (second OUT pin, tied to pin 1 internally); a 10 µF or larger capacitor must be connected between this pin and GND for stability. |
| 3 | FB | input | Feedback input to the control-loop error amplifier that sets the output voltage through the external R1/R2 divider, referenced to the 0.8 V internal reference. |
| 4 | GND | power_in | Device ground, to be connected directly to the thermal pad and not to any external plane. |
| 5 | PG | output | Open-drain power-good output that requires an external 10 kΩ to 100 kΩ pull-up resistor; it may be left floating or tied to GND when unused. |
| 6 | SS_CTRL | input | Soft-start control that sets the NR/SS charging current when tied to GND (≈6.2 µA typ.) or IN (≈100 µA typ.); it must be tied to GND if no NR/SS capacitor is used to avoid output overshoot. |
| 7 | EN | input | Enable input: the regulator is enabled when VEN ≥ VIH(EN) (1.1 V min.) and disabled when VEN ≤ VIL(EN) (0.4 V max.); if enable control is not used, connect it to IN. |
| 8 | NR/SS | passive | Noise-reduction and soft-start pin where an external capacitor (0 to 10 µF recommended range) is connected to filter reference noise and set the output start-up ramp. |
| 9 | IN | power_in | Input supply pin (1.4 V to 6.5 V recommended range) that requires a 10 µF or larger input capacitor. |
| 10 | IN | power_in | Input supply pin (1.4 V to 6.5 V recommended range), paralleled with pin 9, that requires a 10 µF or larger input capacitor. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-10-EP(2.5x2.5) |
| Category | Power Management (PMIC) |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| IN, PG, EN voltage | -0.3 | 7 | V | 4 | |||
| IN, PG, EN voltage (pulse) | -0.3 | 7.5 | V | 5% duty cycle, pulse duration ≤200µs | 4 | ||
| OUT voltage | -0.3 | V | Printed maximum is VIN + 0.3 V (not numeric) | 4 | |||
| SS_CTRL voltage | -0.3 | V | Printed maximum is VIN + 0.3 V (not numeric) | 4 | |||
| NR/SS, FB voltage | -0.3 | 3.6 | V | 4 | |||
| PG sink current | 5 | mA | Current sunk into device | 4 | |||
| Operating junction temperature | TJ | -55 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| ESD human body model | V(ESD) | -2000 | 2000 | V | HBM per ANSI/ESDA/JEDEC JS-001 | 4 | |
| ESD charged device model | V(ESD) | -500 | 500 | V | CDM per JEDEC JESD22-C101 | 4 | |
| Input supply voltage range | VIN | 1.4 | 6.5 | V | 4 | ||
| Output voltage range | VOUT | 0.8 | 5.7 | V | 4 | ||
| Output current | IOUT | 0 | 0.5 | A | 4 | ||
| Input capacitor | CIN | 10 | µF | 4 | |||
| Output capacitor | COUT | 10 | µF | 4 | |||
| Noise-reduction capacitor | CNR/SS | 0 | 10 | µF | 4 | ||
| Feedforward capacitor | CFF | 0 | 100 | nF | 4 | ||
| Power-good pull-up resistor | RPG | 10 | 100 | kΩ | 4 | ||
| Junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Input supply voltage range | VIN | 1.4 | 6.5 | V | 5 | ||
| Input supply UVLO threshold, VIN rising | VUVLO | 1.31 | 1.39 | V | VIN rising | 5 | |
| Output voltage range | VOUT | 0.8 | 5.7 | V | 5 | ||
| Output voltage accuracy | -1 | 1 | % | 1.4V ≤ VIN ≤ 6.5V, 5mA ≤ IOUT ≤ 0.5A | 5 | ||
| Dropout voltage, VIN 1.4V to 5.0V | VDO | 100 | mV | 1.4V ≤ VIN ≤ 5.0V, IOUT = 0.5A, VFB = 0.8V, 3% | 5 | ||
| Dropout voltage, VIN 5.0V to 5.7V | VDO | 200 | mV | 5.0V < VIN ≤ 5.7V, IOUT = 0.5A, VFB = 0.8V, 3% | 5 | ||
| Output current limit | ILIM | 0.8 | 1.1 | 1.5 | A | VOUT forced to 0.9 x VOUT(nom), VIN = VOUT(NOM) + 300mV | 5 |
| GND pin current | IGND | 2.1 | 3.5 | mA | VIN = 6.5V, IOUT = 5mA | 5 | |
| Shutdown GND pin current | ISDN | 0.1 | 15 | µA | PG = open, VIN = 6.5V, VEN = 0.4V | 5 | |
| EN pin current | IEN | -0.2 | 0.2 | µA | VIN = 6.5V, 0V ≤ VEN ≤ 6.5V | 5 | |
| EN pin low-level input voltage (device disabled) | VIL(EN) | 0 | 0.4 | V | Device disabled | 5 | |
| EN pin high-level input voltage (device enabled) | VIH(EN) | 1.1 | 6.5 | V | Device enabled | 5 | |
| SS_CTRL pin current | ISS_CTRL | -0.2 | 0.2 | µA | VIN = 6.5V, 0V ≤ VSS_CTRL ≤ 6.5V | 5 | |
| PG rising threshold | VIT(PG+) | 84 | 90.9 | 95 | % | PG going low as VOUT rises, percent of VOUT(NOM) | 5 |
| PG falling threshold | VIT(PG-) | 82 | 88.9 | 93 | % | PG going low as VOUT falls, percent of VOUT(NOM) | 5 |
| NR/SS charge current | INR/SS | 4 | 6.2 | 9 | µA | VNR/SS = GND, VSS_CTRL = GND | 5 |
| NR/SS charge current | INR/SS | 65 | 100 | 150 | µA | VNR/SS = GND, VSS_CTRL = VIN | 5 |
| FB pin leakage current | IFB | -100 | 100 | nA | VIN = 6.5V, VFB = 0.8V | 6 | |
| Junction-to-ambient thermal resistance | RθJA | 62.5 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 59.7 | °C/W | 4 | |||
| Junction-to-board thermal resistance | RθJB | 30.6 | °C/W | 4 | |||
| Junction-to-top characterization parameter | ψJT | 1.7 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 30.7 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 7.8 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TPS7A9001DSKT - Footprint:
Package_SON:WSON-10-1EP_2.5x2.5mm_P0.5mm_EP1.2x2mm - 3D model: WSON-10-EP(2.5x2.5) (KiCad packages3D, STEP)
- 3D model files:
tps7a9001dskt-etched.step/tps7a9001dskt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a9001dskt.step/tps7a9001dskt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (33 pp, sha256
a1a1adaf3549db90, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).