component
TPS7A8500ARGRT
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, VQFN-20-EP(3.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS7A8500ARGRT
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · VQFN-20-EP(3.5x3.5)
TPS7A8500ARGRT from Texas Instruments, in a VQFN-20-EP(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output pin; 47-μF or larger ceramic capacitor from OUT to ground required for stability and must be placed as close as possible to output. |
| 2 | SNS | input | Output voltage sense input pin; connect to load side of output trace only if ANY-OUT feature is used, otherwise leave floating. |
| 3 | FB | input | Feedback pin connected to error amplifier; 10-nF feed-forward capacitor from FB to OUT recommended to maximize ac performance. |
| 4 | PG | output | Active-high open-drain power-good output indicates when output voltage reaches the target; feed-forward capacitor may disrupt this function. |
| 5 | 50mV | input | ANY-OUT voltage setting pin; connect to ground, SNS, or leave floating; multiple pins may be simultaneously connected to select desired output voltage. |
| 6 | 100mV | input | ANY-OUT voltage setting pin; connect to ground, SNS, or leave floating; multiple pins may be simultaneously connected to select desired output voltage. |
| 7 | 200mV | input | ANY-OUT voltage setting pin; connect to ground, SNS, or leave floating; multiple pins may be simultaneously connected to select desired output voltage. |
| 8 | GND | power_in | Ground pin; must be connected to ground, thermal pad, and each other GND pin with low-impedance connection. |
| 9 | 400mV | input | ANY-OUT voltage setting pin; connect to ground, SNS, or leave floating; multiple pins may be simultaneously connected to select desired output voltage. |
| 10 | 800mV | input | ANY-OUT voltage setting pin; connect to ground, SNS, or leave floating; multiple pins may be simultaneously connected to select desired output voltage. |
| 11 | 1.6V | input | ANY-OUT voltage setting pin; connect to ground, SNS, or leave floating; multiple pins may be simultaneously connected to select desired output voltage. |
| 12 | BIAS | power_in | BIAS supply voltage pin; enables use of low-input voltage, low-output (LILO) voltage conditions; 10-µF capacitor or larger must be connected between this pin and ground if used. |
| 13 | NR/SS | passive | Noise-reduction and soft-start pin; external capacitor between this pin and ground reduces reference voltage noise and enables soft-start function; 10-nF or larger recommended. |
| 14 | EN | input | Enable pin; logic high enables device, logic low disables device; must be connected to IN or BIAS if enable functionality not required. |
| 15 | IN | power_in | Input supply voltage pin; 10-μF or larger ceramic capacitor (5 μF capacitance or greater) from IN to ground required; place input capacitor as close as possible to input. |
| 16 | IN | power_in | Input supply voltage pin; 10-μF or larger ceramic capacitor (5 μF capacitance or greater) from IN to ground required; place input capacitor as close as possible to input. |
| 17 | IN | power_in | Input supply voltage pin; 10-μF or larger ceramic capacitor (5 μF capacitance or greater) from IN to ground required; place input capacitor as close as possible to input. |
| 18 | GND | power_in | Ground pin; must be connected to ground, thermal pad, and each other GND pin with low-impedance connection. |
| 19 | OUT | power_out | Regulated output pin; 47-μF or larger ceramic capacitor from OUT to ground required for stability and must be placed as close as possible to output. |
| 20 | OUT | power_out | Regulated output pin; 47-μF or larger ceramic capacitor from OUT to ground required for stability and must be placed as close as possible to output. |
| 21 | Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20-EP(3.5x3.5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
TPS7A8500ARGRT - Footprint:
Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm - 3D model: VQFN-20-EP(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps7a8500argrt-etched.step/tps7a8500argrt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a8500argrt.step/tps7a8500argrt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (49 pp, sha256
361d696b06535f2b, retrieved 2026-10-06, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).