main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs tps7a8401argrr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
viewers tps7a8401argrr: viewers · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Initial commit: component/tps7a8401argrr · Ray 4d ago
tps7a8401argrr-etched.fit.json tps7a8401argrr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
tps7a8401argrr-etched.glb tps7a8401argrr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
tps7a8401argrr-etched.step tps7a8401argrr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
tps7a8401argrr.glb Publish 0.1.0 · Ray 4d ago
tps7a8401argrr.kicad_mod Publish 0.1.0 · Ray 4d ago
tps7a8401argrr.kicad_sym Publish 0.1.0 · Ray 4d ago
tps7a8401argrr.lbr Publish 0.1.0 · Ray 4d ago
tps7a8401argrr.step Publish 0.1.0 · Ray 4d ago

TPS7A8401ARGRR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · VQFN-20-EP(3.5x3.5)

TPS7A8401ARGRR from Texas Instruments, in a VQFN-20-EP(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT output Regulated output pin; 47-µF or larger ceramic capacitor required from OUT to GND for stability.
2 SNS input Output voltage sense input pin; connect to load side when ANY-OUT feature is used, otherwise leave floating.
3 FB input Feedback pin connected to error amplifier; 10-nF feed-forward capacitor from FB to OUT recommended for optimal AC performance.
4 PG tri_state Open-drain active-high power good output; indicates when output voltage reaches VIT(PG) threshold of target voltage.
5 25mV input ANY-OUT voltage setting pin; connect to GND, SNS, or leave floating to program output voltage with 25-mV resolution.
6 50mV input ANY-OUT voltage setting pin; tie to GND, SNS, or leave floating to select output voltage level.
7 100mV input ANY-OUT voltage setting pin; connect to GND, SNS, or leave open for voltage programming.
8 GND power_in Ground pin; must connect to thermal pad and other GND pins with low-impedance connection.
9 200mV input ANY-OUT voltage setting pin; tie to GND, SNS, or leave floating for output voltage selection.
10 400mV input ANY-OUT voltage setting pin; tie to GND, SNS, or leave floating for output voltage programming.
11 800mV input ANY-OUT voltage setting pin (highest resolution step); connect to GND, SNS, or leave floating.
12 BIAS power_in BIAS supply voltage pin (3.0V to 6.5V); 1-µF or larger capacitor required to GND for LILO operation.
13 NR/SS passive Noise-reduction and soft-start pin; connect external capacitor to GND to reduce reference noise and enable soft-start.
14 EN input Enable control pin (active-high); VIL = 0.5V disables, VIH = 1.1V to 6.5V enables device.
15 IN power_in Input supply voltage pin (1.1V to 6.5V); 10-µF or larger ceramic capacitor required from IN to GND.
16 IN power_in Input supply voltage pin; multiple pins provided to minimize trace impedance.
17 IN power_in Input supply voltage pin; place input capacitors as close as possible to minimize parasitic inductance.
18 GND power_in Ground pin; must connect to thermal pad and other GND pins with low-impedance connection.
19 OUT output Regulated output voltage pin; 47-µF or larger ceramic capacitor required for stability.
20 OUT output Regulated output voltage pin; multiple outputs minimize impedance path to load.
21 Thermal Pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-20-EP(3.5x3.5)
Category Power Management (PMIC)
Pins 21

CAD (KiCad official)

  • Symbol: TPS7A8401ARGRR
  • Footprint: Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm
  • 3D model: VQFN-20-EP(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps7a8401argrr-etched.step / tps7a8401argrr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7a8401argrr.step / tps7a8401argrr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (63 pp, sha256 4d0ce82f384642ef, retrieved 2026-10-01, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF