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TPS7A8401ARGRR
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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, VQFN-20-EP(3.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+58@@ -0,0 +1,58 @@+# TPS7A8401ARGRR++**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · VQFN-20-EP(3.5x3.5)++TPS7A8401ARGRR from Texas Instruments, in a VQFN-20-EP(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OUT | output | Regulated output pin; 47-µF or larger ceramic capacitor required from OUT to GND for stability. |+| 2 | SNS | input | Output voltage sense input pin; connect to load side when ANY-OUT feature is used, otherwise leave floating. |+| 3 | FB | input | Feedback pin connected to error amplifier; 10-nF feed-forward capacitor from FB to OUT recommended for optimal AC performance. |+| 4 | PG | tri_state | Open-drain active-high power good output; indicates when output voltage reaches VIT(PG) threshold of target voltage. |+| 5 | 25mV | input | ANY-OUT voltage setting pin; connect to GND, SNS, or leave floating to program output voltage with 25-mV resolution. |+| 6 | 50mV | input | ANY-OUT voltage setting pin; tie to GND, SNS, or leave floating to select output voltage level. |+| 7 | 100mV | input | ANY-OUT voltage setting pin; connect to GND, SNS, or leave open for voltage programming. |+| 8 | GND | power_in | Ground pin; must connect to thermal pad and other GND pins with low-impedance connection. |+| 9 | 200mV | input | ANY-OUT voltage setting pin; tie to GND, SNS, or leave floating for output voltage selection. |+| 10 | 400mV | input | ANY-OUT voltage setting pin; tie to GND, SNS, or leave floating for output voltage programming. |+| 11 | 800mV | input | ANY-OUT voltage setting pin (highest resolution step); connect to GND, SNS, or leave floating. |+| 12 | BIAS | power_in | BIAS supply voltage pin (3.0V to 6.5V); 1-µF or larger capacitor required to GND for LILO operation. |+| 13 | NR/SS | passive | Noise-reduction and soft-start pin; connect external capacitor to GND to reduce reference noise and enable soft-start. |+| 14 | EN | input | Enable control pin (active-high); VIL = 0.5V disables, VIH = 1.1V to 6.5V enables device. |+| 15 | IN | power_in | Input supply voltage pin (1.1V to 6.5V); 10-µF or larger ceramic capacitor required from IN to GND. |+| 16 | IN | power_in | Input supply voltage pin; multiple pins provided to minimize trace impedance. |+| 17 | IN | power_in | Input supply voltage pin; place input capacitors as close as possible to minimize parasitic inductance. |+| 18 | GND | power_in | Ground pin; must connect to thermal pad and other GND pins with low-impedance connection. |+| 19 | OUT | output | Regulated output voltage pin; 47-µF or larger ceramic capacitor required for stability. |+| 20 | OUT | output | Regulated output voltage pin; multiple outputs minimize impedance path to load. |+| 21 | Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-20-EP(3.5x3.5) |+| Category | Power Management (PMIC) |+| Pins | 21 |++## CAD (KiCad official)++- Symbol: `TPS7A8401ARGRR`+- Footprint: `Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm`+- 3D model: VQFN-20-EP(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `tps7a8401argrr-etched.step` / `tps7a8401argrr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7a8401argrr.step` / `tps7a8401argrr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps7a84a) (63 pp, sha256 `4d0ce82f384642ef`, retrieved 2026-10-01, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps7a8401argrr-datasheet.pdf)
page.jsonadded+235@@ -0,0 +1,235 @@+{+ "slug": "tps7a8401argrr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, VQFN-20-EP(3.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "tps7a8401argrr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps7a8401argrr.kicad_sym",+ "tps7a8401argrr.kicad_mod",+ "tps7a8401argrr.glb",+ "tps7a8401argrr.step",+ "tps7a8401argrr.lbr",+ "docs/hero.png",+ "docs/tps7a8401argrr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "TPS7A8401ARGRR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-20-EP(3.5x3.5)",+ "pin_count": 21,+ "category": "Power Management (PMIC)",+ "subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps7a84a",+ "parts": {+ "symbol": "tps7a8401argrr.kicad_sym",+ "footprint": "tps7a8401argrr.kicad_mod",+ "model_3d": "tps7a8401argrr-etched.glb",+ "model_3d_plain": "tps7a8401argrr.glb",+ "model_3d_step": "tps7a8401argrr-etched.step",+ "model_3d_step_plain": "tps7a8401argrr.step",+ "lbr": "tps7a8401argrr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2866240",+ "digikey": "296-TPS7A8401ARGRRTR-ND",+ "mouser": "595-TPS7A8401ARGRR"+ },+ "distributor_check": {+ "checked_at": "2026-10-01T17:53:51Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-TPS7A8401ARGRRTR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-TPS7A8401ARGRR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "OUT",+ "type": "output",+ "description": "Regulated output pin; 47-µF or larger ceramic capacitor required from OUT to GND for stability."+ },+ {+ "number": "2",+ "name": "SNS",+ "type": "input",+ "description": "Output voltage sense input pin; connect to load side when ANY-OUT feature is used, otherwise leave floating."+ },+ {+ "number": "3",+ "name": "FB",+ "type": "input",+ "description": "Feedback pin connected to error amplifier; 10-nF feed-forward capacitor from FB to OUT recommended for optimal AC performance."+ },+ {+ "number": "4",+ "name": "PG",+ "type": "tri_state",+ "description": "Open-drain active-high power good output; indicates when output voltage reaches VIT(PG) threshold of target voltage."+ },+ {+ "number": "5",+ "name": "25mV",+ "type": "input",+ "description": "ANY-OUT voltage setting pin; connect to GND, SNS, or leave floating to program output voltage with 25-mV resolution."+ },+ {+ "number": "6",+ "name": "50mV",+ "type": "input",+ "description": "ANY-OUT voltage setting pin; tie to GND, SNS, or leave floating to select output voltage level."+ },+ {+ "number": "7",+ "name": "100mV",+ "type": "input",+ "description": "ANY-OUT voltage setting pin; connect to GND, SNS, or leave open for voltage programming."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin; must connect to thermal pad and other GND pins with low-impedance connection."+ },+ {+ "number": "9",+ "name": "200mV",+ "type": "input",+ "description": "ANY-OUT voltage setting pin; tie to GND, SNS, or leave floating for output voltage selection."+ },+ {+ "number": "10",+ "name": "400mV",+ "type": "input",+ "description": "ANY-OUT voltage setting pin; tie to GND, SNS, or leave floating for output voltage programming."+ },+ {+ "number": "11",+ "name": "800mV",+ "type": "input",+ "description": "ANY-OUT voltage setting pin (highest resolution step); connect to GND, SNS, or leave floating."+ },+ {+ "number": "12",+ "name": "BIAS",+ "type": "power_in",+ "description": "BIAS supply voltage pin (3.0V to 6.5V); 1-µF or larger capacitor required to GND for LILO operation."+ },+ {+ "number": "13",+ "name": "NR/SS",+ "type": "passive",+ "description": "Noise-reduction and soft-start pin; connect external capacitor to GND to reduce reference noise and enable soft-start."+ },+ {+ "number": "14",+ "name": "EN",+ "type": "input",+ "description": "Enable control pin (active-high); VIL = 0.5V disables, VIH = 1.1V to 6.5V enables device."+ },+ {+ "number": "15",+ "name": "IN",+ "type": "power_in",+ "description": "Input supply voltage pin (1.1V to 6.5V); 10-µF or larger ceramic capacitor required from IN to GND."+ },+ {+ "number": "16",+ "name": "IN",+ "type": "power_in",+ "description": "Input supply voltage pin; multiple pins provided to minimize trace impedance."+ },+ {+ "number": "17",+ "name": "IN",+ "type": "power_in",+ "description": "Input supply voltage pin; place input capacitors as close as possible to minimize parasitic inductance."+ },+ {+ "number": "18",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin; must connect to thermal pad and other GND pins with low-impedance connection."+ },+ {+ "number": "19",+ "name": "OUT",+ "type": "output",+ "description": "Regulated output voltage pin; 47-µF or larger ceramic capacitor required for stability."+ },+ {+ "number": "20",+ "name": "OUT",+ "type": "output",+ "description": "Regulated output voltage pin; multiple outputs minimize impedance path to load."+ },+ {+ "number": "21",+ "name": "Thermal Pad",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Thermal pad designation: Package documentation refers to 'EXPOSED PAD 21' but official package spec ; ANY-OUT pins (5-7, 9-11): These pins have dual functionality - they can be connected to GND, SNS, or"+ ],+ "pages_sent": 63,+ "cost_usd": 0.5223,+ "at": "2026-10-01T17:53:29"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps7a84a",+ "pages": 63,+ "sha256": "4d0ce82f384642ef",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 21,+ "described": 21,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}