# TPS7A8400ARGRT

**Texas Instruments** · Linear Voltage Regulators (LDO) · VQFN-20-EP(3.5x3.5)

TPS7A8400ARGRT from Texas Instruments, in a VQFN-20-EP(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output pin; requires a 47-µF or larger ceramic capacitor (25 µF capacitance or greater) to ground for stability, placed as close as possible. |
| 2 | SNS | input | Output voltage sense input connecting the internal R1 resistor to the output; connect to the load side only if ANY-OUT is used, otherwise leave floating. |
| 3 | FB | input | Feedback pin connected to the error amplifier; a 10-nF feed-forward capacitor from FB to OUT is recommended but may disrupt Power-Good functionality. |
| 4 | PG | output | Active-high open-drain power-good output that indicates when the output voltage reaches VIT(PG) of the target; a feed-forward capacitor may disrupt PG functionality. |
| 5 | 50mV | input | ANY-OUT 50-mV voltage setting pin; connect to ground, SNS, or leave floating when not in use. |
| 6 | 100mV | input | ANY-OUT 100-mV voltage setting pin; connect to ground, SNS, or leave floating when not in use. |
| 7 | 200mV | input | ANY-OUT 200-mV voltage setting pin; connect to ground, SNS, or leave floating when not in use. |
| 8 | GND | power_in | Ground pin; must be connected to ground, the thermal pad, and the other GND pin with a low-impedance connection. |
| 9 | 400mV | input | ANY-OUT 400-mV voltage setting pin; connect to ground, SNS, or leave floating when not in use. |
| 10 | 800mV | input | ANY-OUT 800-mV voltage setting pin; connect to ground, SNS, or leave floating when not in use. |
| 11 | 1.6V | input | ANY-OUT 1.6-V voltage setting pin; connect to ground, SNS, or leave floating when not in use. |
| 12 | BIAS | power_in | BIAS supply input (3.0 V to 6.5 V) enabling low-input, low-output operation and improving performance for VIN ≤ 2.2 V; needs a 1-µF capacitor to ground, and is left floating or tied to ground if unused. |
| 13 | NR/SS | passive | Noise-reduction and soft-start pin; an external capacitor to ground (10 nF or larger recommended) reduces reference noise and enables soft start. |
| 14 | EN | input | Enable pin; logic high enables the device and logic low disables it, and if unused it must be connected to IN or BIAS. |
| 15 | IN | power_in | Input supply voltage pin (1.1 V to 6.5 V); requires a 10-µF or larger ceramic capacitor (5 µF capacitance or greater) to ground placed close to the pin. |
| 16 | IN | power_in | Input supply voltage pin (1.1 V to 6.5 V); requires a 10-µF or larger ceramic capacitor (5 µF capacitance or greater) to ground placed close to the pin. |
| 17 | IN | power_in | Input supply voltage pin (1.1 V to 6.5 V); requires a 10-µF or larger ceramic capacitor (5 µF capacitance or greater) to ground placed close to the pin. |
| 18 | GND | power_in | Ground pin; must be connected to ground, the thermal pad, and the other GND pin with a low-impedance connection. |
| 19 | OUT | power_out | Regulated output pin; requires a 47-µF or larger ceramic capacitor (25 µF capacitance or greater) to ground for stability, placed as close as possible. |
| 20 | OUT | power_out | Regulated output pin; requires a 47-µF or larger ceramic capacitor (25 µF capacitance or greater) to ground for stability, placed as close as possible. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20-EP(3.5x3.5) |
| Category | Power Supply Chip |
| Pins | 21 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage accuracy | VOUT | -1 |  | 1 | % | 0.8 V ≤ VOUT ≤ 5.15 V, 5 mA ≤ IOUT ≤ 3 A, over VIN | 7 |
| Output voltage accuracy with BIAS | VOUT | -0.75 |  | 0.75 | % | 1.1V ≤ VIN ≤ 2.2 V, 5 mA ≤ IOUT ≤ 3 A, 3.0 V ≤ VBIAS ≤ 6.5 V | 7 |
| Output current limit | ILIM | 3.7 | 4.2 | 4.7 | A | VOUT forced at 0.9 × VOUT(nom), VIN = VOUT(nom) + 0.4 V | 7 |
| Dropout voltage | VDO |  | 155 | 250 | mV | VIN = 1.4 V, IOUT = 3 A, VFB = 0.8 V, 3% | 7 |
| Dropout voltage | VDO |  | 225 | 340 | mV | VIN = 5.4 V, IOUT = 3 A, VFB = 0.8 V, 3% | 7 |
| Dropout voltage | VDO |  | 270 | 450 | mV | VIN = 5.6 V, IOUT = 3 A, VFB = 0.8 V, 3% | 7 |
| Dropout voltage | VDO |  | 110 | 180 | mV | VIN = 1.1 V, VBIAS = 5 V, IOUT = 3 A, VFB = 0.8 V, 3% | 7 |
| GND pin current | IGND |  | 3 | 4 | mA | VIN = 6.5 V, IOUT = 5mA | 7 |
| GND pin current | IGND |  | 4.3 | 5.5 | mA | VIN = 1.4 V, IOUT = 3A | 7 |
| GND pin current in shutdown | IGND |  | 1.2 | 25 | µA | Shutdown, PG = open, VIN = 6.5 V, VEN = 0.5 V | 7 |
| PG pin threshold | VIT(PG) | 82 | 88 | 93 | V | For falling VOUT, % x VOUT | 7 |
| Input supply UVLO with BIAS | VUVLO1(IN) |  | 1.02 | 1.085 | V | VIN rising with VBIAS = 3.0 V | 6 |
| Input supply UVLO without BIAS | VUVLO2(IN) |  | 1.31 | 1.39 | V | VIN rising | 6 |
| Bias supply UVLO | VUVLO(BIAS) |  | 2.83 | 2.9 | V | VBIAS rising, VIN = 1.1 V | 6 |
| EN pin current | IEN | -0.1 |  | 0.1 | µA | VIN = 6.5 V, VEN = 0 V and 6.5 V | 6 |
| BIAS pin current | IBIAS |  | 2.4 | 3.5 | mA | VIN = 1.1 V, VBIAS = 6.5 V, VOUT(nom) = 0.8 V, IOUT = 3 A | 6 |
| EN pin low-level input voltage | VIL(EN) | 0 |  | 0.5 | V | disable device | 6 |
| EN pin high-level input voltage | VIH(EN) | 1.1 |  | 6.5 | V | enable device | 6 |
| PG pin low-level output voltage | VOL(PG) |  |  | 0.4 | V | VOUT < VIT(PG), IPG = -1 mA (current into device) | 6 |
| PG pin leakage current | Ilkg(PG) |  |  | 1 | µA | VOUT > VIT(PG), VPG = 6.5 V | 6 |
| NR/SS pin charging current | INR/SS | 4 | 6.6 | 9 | µA | VNR/SS = GND, VIN = 6.5 V | 6 |
| FB pin leakage current | IFB | -100 |  | 100 | nA | VIN = 6.5 V | 6 |
| Input supply voltage range | VIN | 1.1 |  | 6.5 | V |  | 5 |
| Bias supply voltage range | VBIAS | 3 |  | 6.5 | V |  | 5 |
| Output voltage range | VOUT | 0.8 |  | 5.15 | V | TPS7A8400A | 5 |
| Output current | IOUT | 0 |  | 3 | A |  | 5 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 5 |
| Input capacitor | CIN | 10 | 47 |  | µF |  | 5 |
| Output capacitor | COUT | 47 |  |  | µF | nominal 47 // 10 // 10 | 5 |
| Bias pin capacitor | CBIAS | 1 | 10 |  | µF |  | 5 |
| Power-good pullup resistance | RPG | 10 |  | 100 | kΩ |  | 5 |
| Abs max IN, BIAS, PG, EN voltage |  | -0.3 |  | 7 | V |  | 4 |
| Abs max IN, BIAS, PG, EN pulsed |  | -0.3 |  | 7.5 | V | 5% duty cycle, pulse duration = 200 µs | 4 |
| Abs max SNS, OUT voltage |  | -0.3 |  |  | V | max VIN + 0.3 (or 7.0 V, whichever is smaller) | 4 |
| Abs max NR/SS, FB voltage |  | -0.3 |  | 3.6 | V |  | 4 |
| Abs max ANY-OUT pins voltage |  | -0.3 |  |  | V | max VOUT + 0.3; 50mV to 1.6V pins | 4 |
| Abs max PG sink current |  |  |  | 5 | mA | sink current into device | 4 |
| Abs max operating junction temperature | TJ | -55 |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 4 |
| ESD HBM | V(ESD) | -2000 |  | 2000 | V | Human-body model per ANSI/ESDA/JEDEC JS-001 | 4 |
| ESD CDM | V(ESD) | -500 |  | 500 | V | Charged-device model per JESD22-C101 | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 43.4 |  | °C/W | RGR (VQFN) 20 pins | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 36.8 |  | °C/W |  | 5 |
| Junction-to-board thermal resistance | RθJB |  | 17.6 |  | °C/W |  | 5 |
| Junction-to-top characterization parameter | ψJT |  | 0.8 |  | °C/W |  | 5 |
| Junction-to-board characterization parameter | ψJB |  | 17.6 |  | °C/W |  | 5 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 3.4 |  | °C/W |  | 5 |
| Feedback voltage | VFB |  | 0.8 |  | V |  | 7 |
| Line regulation | ΔVOUT/ΔVIN |  | 0.03 |  | mV/V | IOUT = 5 mA, 1.4 V ≤ VIN ≤ 6.5 V | 7 |
| Output noise voltage | Vn |  | 4.4 |  | μVRMS | BW = 10 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.8 V, VBIAS = 5.0 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF // 10μF // 10μF | 7 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side, copper surface. The use of vias and long traces to the input and output capacitors is stro | 52 |

## CAD (KiCad official)

- Symbol: `TPS7A8400ARGRT`
- Footprint: `Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm`
- 3D model: VQFN-20-EP(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tps7a8400argrt-etched.step` / `tps7a8400argrt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7a8400argrt.step` / `tps7a8400argrt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps7a8400argrt.pdf) (63 pp, sha256 `c7236bbd0f19c107`, retrieved 2026-10-23, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps7a8400argrt-datasheet.pdf)