# TPS7A8300RGWT

**Texas Instruments** · Linear Voltage Regulators (LDO) · VQFN-20-EP(5x5)

TPS7A8300RGWT from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output pin; a 22-µF or larger ceramic capacitor is required for stability (10-µF minimum effective capacitance). |
| 2 | SNS | input | Output voltage sense input; connect this pin only if the ANY-OUT feature is used. |
| 3 | FB | input | Output voltage feedback pin connected to the error amplifier; a 10-nF feed-forward capacitor from FB to OUT is recommended for low-noise applications but may disrupt PG functionality. |
| 4 | PG | output | Active-high open-drain power-good output that indicates when the output voltage reaches 89% of the target; a feed-forward capacitor may disrupt PG functionality. |
| 5 | 50mV | input | ANY-OUT output voltage setting pin; connect to ground to increase the output voltage by 50 mV, or leave floating when not in use. |
| 6 | 100mV | input | ANY-OUT output voltage setting pin; connect to ground to increase the output voltage by 100 mV, or leave floating when not in use. |
| 7 | 200mV | input | ANY-OUT output voltage setting pin; connect to ground to increase the output voltage by 200 mV, or leave floating when not in use. |
| 8 | GND | power_in | Ground pin. |
| 9 | 400mV | input | ANY-OUT output voltage setting pin; connect to ground to increase the output voltage by 400 mV, or leave floating when not in use. |
| 10 | 800mV | input | ANY-OUT output voltage setting pin; connect to ground to increase the output voltage by 800 mV, or leave floating when not in use. |
| 11 | 1.6V | input | ANY-OUT output voltage setting pin; connect to ground to increase the output voltage by 1.6 V, or leave floating when not in use. |
| 12 | BIAS | power_in | BIAS supply voltage pin for use when 1.1 V ≤ VIN ≤ 1.4 V (3.0 V to 6.5 V bias supply), with a 10-µF capacitor connected between this pin and ground. |
| 13 | NR/SS | passive | Noise-reduction and soft-start pin; an external capacitor to ground (10 nF recommended for low noise) reduces reference voltage noise and enables soft-start. |
| 14 | EN | input | Enable pin; logic high enables the device, logic low disables it, and it should not be left floating. |
| 15 | IN | power_in | Input supply voltage pin (1.1 V to 6.5 V); a 10-µF input ceramic capacitor is required. |
| 16 | IN | power_in | Input supply voltage pin (1.1 V to 6.5 V); a 10-µF input ceramic capacitor is required. |
| 17 | IN | power_in | Input supply voltage pin (1.1 V to 6.5 V); a 10-µF input ceramic capacitor is required. |
| 18 | GND | power_in | Ground pin. |
| 19 | OUT | power_out | Regulated output pin; a 22-µF or larger ceramic capacitor is required for stability (10-µF minimum effective capacitance). |
| 20 | OUT | power_out | Regulated output pin; a 22-µF or larger ceramic capacitor is required for stability (10-µF minimum effective capacitance). |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20-EP(5x5) |
| Category | Power Supply Chip |
| Pins | 21 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply voltage range | VIN | 1.1 |  | 6.5 | V |  | 6 |
| Bias supply voltage range | VBIAS | 3 |  | 6.5 | V |  | 6 |
| Input supply UVLO with BIAS | VUVLO1(IN) |  | 1.02 | 1.085 | V | VIN increasing | 6 |
| Input supply UVLO without BIAS | VUVLO2(IN) | 1.31 |  | 1.39 | V | VIN increasing | 6 |
| Bias supply UVLO | VUVLO(BIAS) | 2.83 |  | 2.9 | V | VBIAS increasing | 6 |
| Output voltage range, voltage setting pins | VOUT | 0.8 |  | 3.95 | V | Using voltage setting pins; printed as 0.8, 1.0% to 3.95 + 1.0% | 6 |
| Output voltage range, external resistors | VOUT | 0.8 |  | 5 | V | Using external resistors; printed as 0.8, 1.0% to 5.0 + 1.0% | 6 |
| Output voltage accuracy | VOUT | -1 |  | 1 | % | 0.8 V ≤ VOUT ≤ 5 V, 5 mA ≤ IOUT ≤ 2 A | 6 |
| Dropout voltage (no BIAS) | V(DO) |  |  | 200 | mV | VIN ≥ 1.4 V and VBIAS open, 0.8 V ≤ VOUT ≤ 5.0 V, IOUT = 2 A, VFB = 0.8 V, 3% | 6 |
| Dropout voltage (with BIAS) | V(DO) |  |  | 125 | mV | VIN = 1.1 V, VBIAS = 5.0 V, VOUT(TARGET) = 0.8 V, IOUT = 2 A, VFB = 0.8 V, 3% | 6 |
| Output current limit | I(LIM) | 2.1 | 3.4 | 4.2 | A | VOUT forced at 0.9 × VOUT(TARGET), VIN = VOUT(TARGET) + 300 mV | 6 |
| GND pin current, minimum load | I(GND) |  | 2.8 | 4 | mA | VIN = 6.5 V, no VBIAS supply, IOUT = 5 mA | 6 |
| GND pin current, maximum load | I(GND) |  | 3.7 | 5 | mA | VIN = 1.4 V, no VBIAS supply, IOUT = 2 A | 6 |
| GND pin current, shutdown | I(GND) |  |  | 2.5 | µA | Shutdown, PG = (open), VIN = 6.5 V, no VBIAS supply, V(EN) = 0.5 V | 6 |
| EN pin current | I(EN) | -0.1 |  | 0.1 | µA | VIN = 6.5 V, no VBIAS supply, V(EN) = 0 V and 6.5 V | 6 |
| BIAS pin current | I(BIAS) |  | 2.3 | 3.5 | mA | VIN = 1.1 V, VBIAS = 6.5 V, VOUT(TARGET) = 0.8 V, IOUT = 2 A | 6 |
| EN pin low-level input voltage (disable) | VIL(EN) | 0 |  | 0.5 | V |  | 6 |
| EN pin high-level input voltage (enable) | VIH(EN) | 1.1 |  | 6.5 | V |  | 6 |
| PG pin threshold | VIT(PG) | 0.82 | 0.872 | 0.93 | VOUT | For the direction PG↓ with decreasing VOUT | 7 |
| PG pin low-level output voltage | VOL(PG) |  |  | 0.4 | V | VOUT < VIT(PG), IPG = -1 mA (current into device) | 7 |
| PG pin leakage current | Ilkg(PG) |  |  | 1 | µA | VOUT > VIT(PG), V(PG) = 6.5 V | 7 |
| NR/SS pin charging current | I(NR/SS) | 4 | 6.2 | 9 | µA | VNR/SS = GND, VIN = 6.5 V | 7 |
| FB pin leakage current | IFB | -100 |  | 100 | nA | VIN = 6.5 V | 7 |
| Operating junction temperature (electrical table) | TJ | -40 |  | 125 | °C |  | 7 |
| Reference voltage | V(REF) |  | 0.8 |  | V | V(REF) = V(FB) = V(NR/SS) | 6 |
| Line regulation | ΔVO(ΔVI) |  | 0.003 |  | %/V | IOUT = 5 mA, 1.4 V ≤ VIN ≤ 6.5 V | 6 |
| Load regulation | ΔVO(ΔIO) |  | 0.0001 |  | %/A | 5 mA ≤ IOUT ≤ 2 A | 6 |
| Power-supply ripple rejection | PSRR |  | 40 |  | dB | f = 1 MHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 2 A, CNR/SS = 10 nF, CFF = 10 nF | 7 |
| Output noise voltage | Vn |  | 6 |  | µVRMS | BW = 10 Hz to 100 kHz, VIN = 1.4 V, VOUT = 0.8 V, IOUT = 1.5 A, CNR/SS = 10 nF, CFF = 10 nF | 7 |
| Thermal shutdown temperature | Tsd |  | 160 |  | °C | Shutdown, temperature increasing | 7 |
| Thermal shutdown reset temperature | Tsd |  | 140 |  | °C | Reset, temperature decreasing | 7 |
| Input supply voltage range | VIN | 1.1 |  | 6.5 | V |  | 5 |
| Bias supply voltage range | VBIAS | 3 |  | 6.5 | V | Required when VIN below 1.4 V | 5 |
| Output current | IOUT | 0 |  | 2 | A |  | 5 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 5 |
| IN, BIAS, PG, EN voltage |  | -0.3 |  | 7 | V |  | 5 |
| IN, BIAS, PG, EN voltage (5% duty cycle) |  | -0.3 |  | 7.5 | V | 5% duty cycle | 5 |
| SNS, OUT voltage |  | -0.3 |  |  | V | Max is VIN + 0.3 V (or 7.0 V, whichever is smaller) | 5 |
| NR/SS, FB voltage |  | -0.3 |  | 3.6 | V |  | 5 |
| Output setting pins voltage (50mV...1.6V) |  | -0.3 |  |  | V | Max is VOUT + 0.3 V | 5 |
| PG sink current into device |  |  |  | 5 | mA |  | 5 |
| Operating junction temperature | TJ | -55 |  | 150 | °C |  | 5 |
| Storage temperature range | Tstg | -55 |  | 150 | °C |  | 5 |
| ESD HBM | V(ESD) | -2 |  | 2 | kV | Human body model, all pins | 5 |
| ESD CDM | V(ESD) | -500 |  | 500 | V | Charged device model, all pins | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 33.6 |  | °C/W | RGW (QFN) 20 pins | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 30 |  | °C/W | RGW (QFN) 20 pins | 5 |
| Junction-to-board thermal resistance | RθJB |  | 14 |  | °C/W | RGW (QFN) 20 pins | 5 |
| Junction-to-top characterization parameter | ψJT |  | 0.2 |  | °C/W | RGW (QFN) 20 pins | 5 |
| Junction-to-board characterization parameter | ψJB |  | 14 |  | °C/W | RGW (QFN) 20 pins | 5 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 1.6 |  | °C/W | RGW (QFN) 20 pins | 5 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is stron | 32 |

## CAD (KiCad official)

- Symbol: `TPS7A8300RGWT`
- Footprint: `Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm`
- 3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `tps7a8300rgwt-etched.step` / `tps7a8300rgwt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7a8300rgwt.step` / `tps7a8300rgwt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps7a8300) (47 pp, sha256 `31bc3e5222f7a645`, retrieved 2026-10-27, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps7a8300rgwt-datasheet.pdf)