component
TPS7A7200RGWT
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, VQFN-20-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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TPS7A7200RGWT
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · VQFN-20-EP(5x5)
TPS7A7200RGWT from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output pin; a 4.7-µF or larger capacitance is required for stability. |
| 2 | SNS | input | Output voltage sense input pin used with the FB pin in the user-configurable output voltage setting. |
| 3 | FB | input | Output voltage feedback pin connected to the error amplifier; connect a 220-pF ceramic capacitor from FB to OUT. |
| 4 | PG | output | Active-high power-good open-drain output that indicates when the output voltage reaches 90% of the target. |
| 5 | 50mV | input | Output voltage setting pin that must be connected to ground or left floating; grounding it increases VOUT by 50 mV. |
| 6 | 100mV | input | Output voltage setting pin that must be connected to ground or left floating; grounding it increases VOUT by 100 mV. |
| 7 | 200mV | input | Output voltage setting pin that must be connected to ground or left floating; grounding it increases VOUT by 200 mV. |
| 8 | GND | power_in | Ground pin. |
| 9 | 400mV | input | Output voltage setting pin that must be connected to ground or left floating; grounding it increases VOUT by 400 mV. |
| 10 | 800mV | input | Output voltage setting pin that must be connected to ground or left floating; grounding it increases VOUT by 800 mV. |
| 11 | 1.6V | input | Output voltage setting pin that must be connected to ground or left floating; grounding it increases VOUT by 1.6 V. |
| 12 | NC | unconnected | Not internally connected; this pin must be connected to a large-area ground plane. |
| 13 | SS | passive | Soft-start pin; leaving it open gives the default soft start, and an external capacitor to ground enables an RC-delay soft start. |
| 14 | EN | input | Enable pin; driving it to logic high enables the device and driving it to logic low disables the device. |
| 15 | IN | power_in | Unregulated supply voltage pin; connect an input capacitor to this pin. |
| 16 | IN | power_in | Unregulated supply voltage pin; connect an input capacitor to this pin. |
| 17 | IN | power_in | Unregulated supply voltage pin; connect an input capacitor to this pin. |
| 18 | GND | power_in | Ground pin. |
| 19 | OUT | power_out | Regulated output pin; a 4.7-µF or larger capacitance is required for stability. |
| 20 | OUT | power_out | Regulated output pin; a 4.7-µF or larger capacitance is required for stability. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VIN | 1.425 | 6.5 | V | 4 | ||
| Output voltage | VOUT | 0.9 | 5 | V | 4 | ||
| Enable voltage | VEN | 0 | 6.5 | V | 4 | ||
| Pullup voltage | VPG | 0 | 6.5 | V | 4 | ||
| Any-out voltage (50 mV, 100 mV, 200 mV, 400 mV, 800 mV, 1.6 V pins) | 0 | V | maximum printed as VOUT | 4 | |||
| Output current | IOUT | 0 | 2 | A | 4 | ||
| Output capacitance | COUT | 4.7 | 200 | µF | for COUT above 47 µF a CFF of at least 220 pF must be used | 4 | |
| Feedforward capacitance | CF | 0 | 100 | nF | 4 | ||
| Junction temperature (recommended operating) | TJ | -40 | 125 | °C | 4 | ||
| IN, PG, EN voltage | -0.3 | 7 | V | 4 | |||
| SS, FB, SNS, OUT voltage | -0.3 | V | maximum printed as VIN + 0.3 V (or +7 V, whichever is smaller) | 4 | |||
| 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, 1.6 V pins voltage | -0.3 | V | maximum printed as VOUT + 0.3 V | 4 | |||
| PG sink current into IC | 5 | mA | 4 | ||||
| Operating virtual junction temperature | TJ | -55 | 160 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| Input voltage range | VIN | 1.425 | 6.5 | V | 6 | ||
| Output voltage range (adjustable) | VOUT | 0.9 | 5 | V | Adjustable with external feedback resistors | 6 | |
| Output voltage range (fixed) | VOUT | 0.9 | 3.5 | V | Fixed with voltage setting pins | 6 | |
| Output voltage accuracy (adjustable) | -2 | 2 | % | Adjustable, 25 mA ≤ IOUT ≤ 2 A | 6 | ||
| Output voltage accuracy (fixed) | -3 | 3 | % | Fixed, 25 mA ≤ IOUT ≤ 2 A | 6 | ||
| Line regulation | ΔVO(ΔVI) | 0.01 | %/V | IOUT = 25 mA | 6 | ||
| Load regulation | ΔVO(ΔIO) | 0.1 | %/A | 25 mA ≤ IOUT ≤ 2 A | 6 | ||
| Dropout voltage (VOUT ≤ 3.3 V) | V(DO) | 180 | mV | VOUT ≤ 3.3 V, IOUT = 2 A, V(FB) = GND | 6 | ||
| Dropout voltage (3.3 V < VOUT) | V(DO) | 470 | mV | 3.3 V < VOUT, IOUT = 2 A, V(FB) = GND | 6 | ||
| Output current limit | I(LIM) | 2.4 | 3.1 | A | VOUT forced at 0.9 × VOUT(TARGET), VIN = 3.3 V, VOUT(TARGET) = 0.9 V | 6 | |
| GND pin current at full load | I(GND) | 2.6 | mA | Full load, IOUT = 2 A | 6 | ||
| GND pin current at minimum load | I(GND) | 4 | mA | VIN = 6.5 V, VOUT(TARGET) = 0.9 V, IOUT = 25 mA | 6 | ||
| GND pin current in shutdown | I(GND) | 0.1 | 5 | µA | Shutdown, PG = (open), VIN = 6.5 V, VOUT(TARGET) = 0.9 V, V(EN) < 0.5 V | 6 | |
| EN pin current | I(EN) | -0.1 | 0.1 | µA | VIN = 6.5 V, V(EN) = 0 V and 6.5 V | 6 | |
| EN pin low-level input voltage (disable device) | VIL(EN) | 0 | 0.5 | V | 6 | ||
| EN pin high-level input voltage (enable device) | VIH(EN) | 1.1 | 6.5 | V | 6 | ||
| PG pin threshold | VIT(PG) | 0.85 | 0.9 | 0.96 | VOUT | For the direction PG↓ with decreasing VOUT | 6 |
| PG pin hysteresis | Vhys(PG) | 0.02 | VOUT | For PG↑ | 6 | ||
| PG pin low-level output voltage | VOL(PG) | 0.4 | V | VOUT < VIT(PG), IPG = -1 mA (current into device) | 6 | ||
| PG pin leakage current | Ilkg(PG) | 1 | µA | VOUT > VIT(PG), V(PG) = 6.5 V | 6 | ||
| SS pin charging current | I(SS) | 3.5 | 5.1 | 7.2 | µA | V(SS) = GND, VIN = 3.3 V | 6 |
| Output noise voltage | Vn | 40.65 | µVRMS | BW = 100 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.2 V, IOUT = 2 A | 6 | ||
| Thermal shutdown temperature (shutdown, increasing) | Tsd | 160 | °C | Shutdown, temperature increasing | 6 | ||
| Thermal shutdown temperature (reset, decreasing) | Tsd | 140 | °C | Reset, temperature decreasing | 6 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 6 | ||
| SS pin voltage | V(SS) | 0.5 | V | 6 | |||
| Junction-to-ambient thermal resistance | RθJA | 35.7 | °C/W | RGW (VQFN, 20 pins) | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 33.6 | °C/W | RGW (VQFN, 20 pins) | 5 | ||
| Junction-to-board thermal resistance | RθJB | 15.2 | °C/W | RGW (VQFN, 20 pins) | 5 | ||
| Junction-to-top characterization parameter | ψJT | 0.4 | °C/W | RGW (VQFN, 20 pins) | 5 | ||
| Junction-to-board characterization parameter | ψJB | 15.4 | °C/W | RGW (VQFN, 20 pins) | 5 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 3.8 | °C/W | RGW (VQFN, 20 pins) | 5 |
CAD (KiCad official)
- Symbol:
TPS7A7200RGWT - Footprint:
Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm - 3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps7a7200rgwt-etched.step/tps7a7200rgwt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a7200rgwt.step/tps7a7200rgwt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (45 pp, sha256
02a39262543199db, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).