component
TPS7A7200QRGWREP
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Texas Instruments Linear Voltage Regulators (LDO), VQFN-20-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS7A7200QRGWREP
Texas Instruments · Linear Voltage Regulators (LDO) · VQFN-20-EP(5x5)
TPS7A7200QRGWREP from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output pin; a 4.7-μF or larger capacitance is required for stability. |
| 2 | SNS | input | Output voltage sense input pin used in the user-configurable and traditional adjustable output voltage configurations. |
| 3 | FB | input | Output voltage feedback pin connected to the error amplifier, and a 220-pF ceramic capacitor from FB to OUT is highly recommended. |
| 4 | PG | output | Active-high open-drain power good output that indicates when the output voltage reaches 90% of target, with a maximum sink current of 5 mA. |
| 5 | 50mV | input | Output voltage setting pin that adds 50 mV to the output when connected to ground, and should be grounded or left floating. |
| 6 | 100mV | input | Output voltage setting pin that adds 100 mV to the output when connected to ground, and should be grounded or left floating. |
| 7 | 200mV | input | Output voltage setting pin that adds 200 mV to the output when connected to ground, and should be grounded or left floating. |
| 8 | GND | power_in | Ground pin. |
| 9 | 400mV | input | Output voltage setting pin that adds 400 mV to the output when connected to ground, and should be grounded or left floating. |
| 10 | 800mV | input | Output voltage setting pin that adds 800 mV to the output when connected to ground, and should be grounded or left floating. |
| 11 | 1.6V | input | Output voltage setting pin that adds 1.6 V to the output when connected to ground, and should be grounded or left floating. |
| 12 | NC | unconnected | Not internally connected; it is strongly recommended to connect this pin and the thermal pad to a large-area ground plane. |
| 13 | SS | input | Soft-start pin; leaving it open gives the default soft-start, and an external capacitor to ground enables an RC-delay soft-start. |
| 14 | EN | input | Enable pin; driving it to logic high enables the device and driving it to logic low disables the device. |
| 15 | IN | power_in | Unregulated supply voltage pin, to which an input capacitor is recommended. |
| 16 | IN | power_in | Unregulated supply voltage pin, to which an input capacitor is recommended. |
| 17 | IN | power_in | Unregulated supply voltage pin, to which an input capacitor is recommended. |
| 18 | GND | power_in | Ground pin. |
| 19 | OUT | power_out | Regulated output pin; a 4.7-μF or larger capacitance is required for stability. |
| 20 | OUT | power_out | Regulated output pin; a 4.7-μF or larger capacitance is required for stability. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20-EP(5x5) |
| Category | Power Supply Chip |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 1.425 | 6.5 | V | 4 | ||
| Output voltage range (adjustable with external feedback resistors) | VOUT | 0.9 | 5 | V | Adjustable with external feedback resistors | 4 | |
| Output voltage range (fixed with voltage setting pins) | VOUT | 0.9 | 3.5 | V | Fixed with voltage setting pins | 4 | |
| Output voltage accuracy (adjustable) | VOUT | -2 | 2 | % | Adjustable, 25 mA ≤ IOUT ≤ 2 A | 4 | |
| Output voltage accuracy (fixed) | VOUT | -3 | 3 | % | Fixed, 25 mA ≤ IOUT ≤ 2 A | 4 | |
| Line regulation | ΔVO(ΔVI) | 0.01 | %/V | IOUT = 25 mA | 4 | ||
| Load regulation | ΔVO(ΔIO) | 0.1 | %/A | 25 mA ≤ IOUT ≤ 2 A | 4 | ||
| Dropout voltage (VOUT ≤ 3.3 V) | V(DO) | 180 | mV | VOUT ≤ 3.3 V, IOUT = 2 A, V(FB) = GND | 4 | ||
| Dropout voltage (3.3 V < VOUT) | V(DO) | 470 | mV | 3.3 V < VOUT, IOUT = 2 A, V(FB) = GND | 4 | ||
| Output current limit | I(LIM) | 2.4 | 3.1 | A | VOUT forced at 0.9 × VOUT(TARGET), VIN = 3.3 V, VOUT(TARGET) = 0.9 V | 4 | |
| GND pin current (full load) | I(GND) | 2.6 | mA | Full load, IOUT = 2 A | 4 | ||
| GND pin current (minimum load) | I(GND) | 4 | mA | Minimum load, VIN = 6.5 V, VOUT(TARGET) = 0.9 V, IOUT = 25 mA | 4 | ||
| Shutdown current (PG open) | I(GND) | 0.1 | 5 | μA | Shutdown, PG = (open), VIN = 6.5 V, VOUT(TARGET) = 0.9 V, V(EN) < 0.5 V | 4 | |
| EN pin current | I(EN) | -0.1 | 0.1 | μA | VIN = 6.5 V, V(EN) = 0 V and 6.5 V | 4 | |
| EN pin low-level input voltage (disable device) | VIL(EN) | 0 | 0.5 | V | Disable device | 4 | |
| EN pin high-level input voltage (enable device) | VIH(EN) | 1.1 | 6.5 | V | Enable device | 4 | |
| PG pin threshold | VIT(PG) | 0.85 | 0.9 | 0.96 | VOUT | For the direction PG↓ with decreasing VOUT | 4 |
| PG pin hysteresis | Vhys(PG) | 0.02 | V | For PG↑; value in units of VOUT | 4 | ||
| PG pin low-level output voltage | VOL(PG) | 0.4 | V | VOUT < VIT(PG), IPG = -1 mA (current into device) | 4 | ||
| PG pin leakage current | Ilkg(PG) | 1 | μA | VOUT > VIT(PG), V(PG) = 6.5 V | 4 | ||
| SS pin charging current | I(SS) | 3.5 | 5.1 | 7.2 | μA | V(SS) = GND, VIN = 3.3 V | 4 |
| Thermal shutdown temperature (shutdown, increasing) | Tsd | 160 | °C | Shutdown, temperature increasing | 4 | ||
| Thermal shutdown temperature (reset, decreasing) | Tsd | 140 | °C | Reset, temperature decreasing | 4 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Input voltage (IN, PG, EN) absolute maximum | -0.3 | 7 | V | IN, PG, EN | 3 | ||
| Voltage SS, FB, SNS, OUT absolute maximum | -0.3 | V | SS, FB, SNS, OUT; VIN + 0.3 V (see note 2) | 3 | |||
| Voltage 50mV, 100mV, 200mV, 400mV, 800mV, 1.6V pins absolute maximum | -0.3 | V | VOUT + 0.3 V | 3 | |||
| PG sink current into IC absolute maximum | 5 | mA | PG (sink current into IC) | 3 | |||
| Junction temperature absolute maximum | TJ | -40 | 150 | °C | 3 | ||
| Storage temperature | Tstg | -40 | 150 | °C | 3 | ||
| HBM ESD rating | 2 | kV | Human body model (HBM, JESD22-A114A) | 3 | |||
| CDM ESD rating | 500 | V | Charged device model (CDM, JESD22-C101B.01) | 3 | |||
| Junction-to-ambient thermal resistance | θJA | 35.7 | °C/W | RGW 20 pins, natural convection, JEDEC high-K board | 3 | ||
| Junction-to-case (top) thermal resistance | θJCtop | 33.6 | °C/W | RGW 20 pins | 3 | ||
| Junction-to-board thermal resistance | θJB | 15.2 | °C/W | RGW 20 pins | 3 | ||
| Junction-to-top characterization parameter | ψJT | 0.4 | °C/W | RGW 20 pins | 3 | ||
| Junction-to-board characterization parameter | ψJB | 15.4 | °C/W | RGW 20 pins | 3 | ||
| Junction-to-case (bottom) thermal resistance | θJCbot | 3.8 | °C/W | RGW 20 pins | 3 |
CAD (KiCad official)
- Symbol:
TPS7A7200QRGWREP - Footprint:
Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm - 3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps7a7200qrgwrep-etched.step/tps7a7200qrgwrep-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a7200qrgwrep.step/tps7a7200qrgwrep.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
803d48a51183ca09, retrieved 2026-11-05, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS7A7200QRGWREP
**Texas Instruments** · Linear Voltage Regulators (LDO) · VQFN-20-EP(5x5)
TPS7A7200QRGWREP from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output pin; a 4.7-μF or larger capacitance is required for stability. |
| 2 | SNS | input | Output voltage sense input pin used in the user-configurable and traditional adjustable output voltage configurations. |
| 3 | FB | input | Output voltage feedback pin connected to the error amplifier, and a 220-pF ceramic capacitor from FB to OUT is highly recommended. |
| 4 | PG | output | Active-high open-drain power good output that indicates when the output voltage reaches 90% of target, with a maximum sink current of 5 mA. |
| 5 | 50mV | input | Output voltage setting pin that adds 50 mV to the output when connected to ground, and should be grounded or left floating. |
| 6 | 100mV | input | Output voltage setting pin that adds 100 mV to the output when connected to ground, and should be grounded or left floating. |
| 7 | 200mV | input | Output voltage setting pin that adds 200 mV to the output when connected to ground, and should be grounded or left floating. |
| 8 | GND | power_in | Ground pin. |
| 9 | 400mV | input | Output voltage setting pin that adds 400 mV to the output when connected to ground, and should be grounded or left floating. |
| 10 | 800mV | input | Output voltage setting pin that adds 800 mV to the output when connected to ground, and should be grounded or left floating. |
| 11 | 1.6V | input | Output voltage setting pin that adds 1.6 V to the output when connected to ground, and should be grounded or left floating. |
| 12 | NC | unconnected | Not internally connected; it is strongly recommended to connect this pin and the thermal pad to a large-area ground plane. |
| 13 | SS | input | Soft-start pin; leaving it open gives the default soft-start, and an external capacitor to ground enables an RC-delay soft-start. |
| 14 | EN | input | Enable pin; driving it to logic high enables the device and driving it to logic low disables the device. |
| 15 | IN | power_in | Unregulated supply voltage pin, to which an input capacitor is recommended. |
| 16 | IN | power_in | Unregulated supply voltage pin, to which an input capacitor is recommended. |
| 17 | IN | power_in | Unregulated supply voltage pin, to which an input capacitor is recommended. |
| 18 | GND | power_in | Ground pin. |
| 19 | OUT | power_out | Regulated output pin; a 4.7-μF or larger capacitance is required for stability. |
| 20 | OUT | power_out | Regulated output pin; a 4.7-μF or larger capacitance is required for stability. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20-EP(5x5) |
| Category | Power Supply Chip |
| Pins | 21 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 1.425 | | 6.5 | V | | 4 |
| Output voltage range (adjustable with external feedback resistors) | VOUT | 0.9 | | 5 | V | Adjustable with external feedback resistors | 4 |
| Output voltage range (fixed with voltage setting pins) | VOUT | 0.9 | | 3.5 | V | Fixed with voltage setting pins | 4 |
| Output voltage accuracy (adjustable) | VOUT | -2 | | 2 | % | Adjustable, 25 mA ≤ IOUT ≤ 2 A | 4 |
| Output voltage accuracy (fixed) | VOUT | -3 | | 3 | % | Fixed, 25 mA ≤ IOUT ≤ 2 A | 4 |
| Line regulation | ΔVO(ΔVI) | | 0.01 | | %/V | IOUT = 25 mA | 4 |
| Load regulation | ΔVO(ΔIO) | | 0.1 | | %/A | 25 mA ≤ IOUT ≤ 2 A | 4 |
| Dropout voltage (VOUT ≤ 3.3 V) | V(DO) | | 180 | | mV | VOUT ≤ 3.3 V, IOUT = 2 A, V(FB) = GND | 4 |
| Dropout voltage (3.3 V < VOUT) | V(DO) | | 470 | | mV | 3.3 V < VOUT, IOUT = 2 A, V(FB) = GND | 4 |
| Output current limit | I(LIM) | 2.4 | 3.1 | | A | VOUT forced at 0.9 × VOUT(TARGET), VIN = 3.3 V, VOUT(TARGET) = 0.9 V | 4 |
| GND pin current (full load) | I(GND) | | 2.6 | | mA | Full load, IOUT = 2 A | 4 |
| GND pin current (minimum load) | I(GND) | | 4 | | mA | Minimum load, VIN = 6.5 V, VOUT(TARGET) = 0.9 V, IOUT = 25 mA | 4 |
| Shutdown current (PG open) | I(GND) | | 0.1 | 5 | μA | Shutdown, PG = (open), VIN = 6.5 V, VOUT(TARGET) = 0.9 V, V(EN) < 0.5 V | 4 |
| EN pin current | I(EN) | -0.1 | | 0.1 | μA | VIN = 6.5 V, V(EN) = 0 V and 6.5 V | 4 |
| EN pin low-level input voltage (disable device) | VIL(EN) | 0 | | 0.5 | V | Disable device | 4 |
| EN pin high-level input voltage (enable device) | VIH(EN) | 1.1 | | 6.5 | V | Enable device | 4 |
| PG pin threshold | VIT(PG) | 0.85 | 0.9 | 0.96 | VOUT | For the direction PG↓ with decreasing VOUT | 4 |
| PG pin hysteresis | Vhys(PG) | | 0.02 | | V | For PG↑; value in units of VOUT | 4 |
| PG pin low-level output voltage | VOL(PG) | | | 0.4 | V | VOUT < VIT(PG), IPG = -1 mA (current into device) | 4 |
| PG pin leakage current | Ilkg(PG) | | | 1 | μA | VOUT > VIT(PG), V(PG) = 6.5 V | 4 |
| SS pin charging current | I(SS) | 3.5 | 5.1 | 7.2 | μA | V(SS) = GND, VIN = 3.3 V | 4 |
| Thermal shutdown temperature (shutdown, increasing) | Tsd | | 160 | | °C | Shutdown, temperature increasing | 4 |
| Thermal shutdown temperature (reset, decreasing) | Tsd | | 140 | | °C | Reset, temperature decreasing | 4 |
| Operating junction temperature | TJ | -40 | | 125 | °C | | 4 |
| Input voltage (IN, PG, EN) absolute maximum | | -0.3 | | 7 | V | IN, PG, EN | 3 |
| Voltage SS, FB, SNS, OUT absolute maximum | | -0.3 | | | V | SS, FB, SNS, OUT; VIN + 0.3 V (see note 2) | 3 |
| Voltage 50mV, 100mV, 200mV, 400mV, 800mV, 1.6V pins absolute maximum | | -0.3 | | | V | VOUT + 0.3 V | 3 |
| PG sink current into IC absolute maximum | | | | 5 | mA | PG (sink current into IC) | 3 |
| Junction temperature absolute maximum | TJ | -40 | | 150 | °C | | 3 |
| Storage temperature | Tstg | -40 | | 150 | °C | | 3 |
| HBM ESD rating | | | | 2 | kV | Human body model (HBM, JESD22-A114A) | 3 |
| CDM ESD rating | | | | 500 | V | Charged device model (CDM, JESD22-C101B.01) | 3 |
| Junction-to-ambient thermal resistance | θJA | | 35.7 | | °C/W | RGW 20 pins, natural convection, JEDEC high-K board | 3 |
| Junction-to-case (top) thermal resistance | θJCtop | | 33.6 | | °C/W | RGW 20 pins | 3 |
| Junction-to-board thermal resistance | θJB | | 15.2 | | °C/W | RGW 20 pins | 3 |
| Junction-to-top characterization parameter | ψJT | | 0.4 | | °C/W | RGW 20 pins | 3 |
| Junction-to-board characterization parameter | ψJB | | 15.4 | | °C/W | RGW 20 pins | 3 |
| Junction-to-case (bottom) thermal resistance | θJCbot | | 3.8 | | °C/W | RGW 20 pins | 3 |
## CAD (KiCad official)
- Symbol: `TPS7A7200QRGWREP`
- Footprint: `Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm`
- 3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `tps7a7200qrgwrep-etched.step` / `tps7a7200qrgwrep-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7a7200qrgwrep.step` / `tps7a7200qrgwrep.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps7a7200-ep) (29 pp, sha256 `803d48a51183ca09`, retrieved 2026-11-05, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps7a7200qrgwrep-datasheet.pdf)