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TPS7A7100RGTT

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps7a7100rgttfactory-2.0.0extractor-text

Verified TPS7A7100RGTT

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS7A7100RGTT · VQFN-16-EP(3x3) · 17 pins
  • ✓copper: 17 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 45-page datasheet
  • ✓distributor: lcsc C2867077, digikey 296-35674-2-ND, mouser 595-TPS7A7100RGTT
  • ✓family: QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-oqwks9aq/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps7a7100rgtt.kicad_sym✓ tps7a7100rgtt.kicad_mod✓ tps7a7100rgtt.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers tps7a7100rgtt: viewers · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
tps7a7100rgtt-etched.glb Publish 0.1.0 · Ray 1d ago
tps7a7100rgtt-etched.step tps7a7100rgtt: factory component page (tier=mfr) · Ray 1d ago
tps7a7100rgtt-hero.glb tps7a7100rgtt: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
tps7a7100rgtt-hero.overlay.json Publish 0.1.0 · Ray 1d ago
tps7a7100rgtt.glb Publish 0.1.0 · Ray 1d ago
tps7a7100rgtt.kicad_mod Publish 0.1.0 · Ray 1d ago
tps7a7100rgtt.kicad_sym Publish 0.1.0 · Ray 1d ago
tps7a7100rgtt.lbr Publish 0.1.0 · Ray 1d ago
tps7a7100rgtt.step Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier mfr, 17 pins · Ray 1d ago

TPS7A7100RGTT

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · VQFN-16-EP(3x3)

TPS7A7100RGTT from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SNS input Output voltage sense input pin used for the User-Configurable Output Voltage setting.
2 FB input Output voltage feedback pin connected to the error amplifier, with a 220-pF ceramic capacitor recommended from FB to OUT.
3 PG output Active-high open-drain power-good output that indicates when the output voltage reaches 90% of the target.
4 50mV input Output voltage setting pin that must be connected to ground or left floating, and connecting it to GND increases VOUT by 50 mV.
5 100mV input Output voltage setting pin that must be connected to ground or left floating, and connecting it to GND increases VOUT by 100 mV.
6 200mV input Output voltage setting pin that must be connected to ground or left floating, and connecting it to GND increases VOUT by 200 mV.
7 GND power_in Ground pin for the device.
8 400mV input Output voltage setting pin that must be connected to ground or left floating, and connecting it to GND increases VOUT by 400 mV.
9 800mV input Output voltage setting pin that must be connected to ground or left floating, and connecting it to GND increases VOUT by 800 mV.
10 1.6V input Output voltage setting pin that must be connected to ground or left floating, and connecting it to GND increases VOUT by 1.6 V.
11 SS passive Soft-start pin; leaving it open gives the default soft start, and an external capacitor to ground sets an RC-delay soft start.
12 EN input Enable pin where logic high enables the device and logic low disables it.
13 IN power_in Unregulated supply voltage pin that requires an input capacitor, with VIN specified from 1.425 V to 6.5 V.
14 IN power_in Unregulated supply voltage pin that requires an input capacitor, with VIN specified from 1.425 V to 6.5 V.
15 OUT power_out Regulated output pin that requires a 4.7-µF or larger capacitance for stability.
16 OUT power_out Regulated output pin that requires a 4.7-µF or larger capacitance for stability.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN 1.425 6.5 V 6
Output voltage, adjustable VOUT 0.9 5 V Adjustable with external feedback resistors 6
Output voltage, fixed VOUT 0.9 3.5 V Fixed with voltage setting pins 6
Output voltage accuracy, RGT adjustable -1.5 1.5 % RGT package only, adjustable, -40°C ≤ TA ≤ 85°C, 25 mA ≤ IOUT ≤ 1 A 6
Output voltage accuracy, RGT fixed -2 2 % RGT package only, fixed, -40°C ≤ TA ≤ 85°C, 25 mA ≤ IOUT ≤ 1 A 6
Output voltage accuracy, adjustable -2 2 % Adjustable, 25 mA ≤ IOUT ≤ 1 A 6
Output voltage accuracy, fixed -3 3 % Fixed, 25 mA ≤ IOUT ≤ 1 A 6
Output current limit I(LIM) 1.1 1.6 A VOUT forced at 0.9 × VOUT(TARGET), VIN = 3.3 V, VOUT(TARGET) = 0.9 V 6
EN pin current I(EN) -0.1 0.1 µA VIN = 6.5 V, V(EN) = 0 V and 6.5 V 6
EN pin low-level input voltage VIL(EN) 0.5 V Disable device 6
EN pin high-level input voltage VIH(EN) 1.1 6.5 V Enable device 6
PG pin threshold VIT(PG) 0.85 0.9 0.96 VOUT For the direction PG↓ with decreasing VOUT 6
PG pin hysteresis Vhys(PG) 0.02 VOUT For PG↑ 6
PG pin low-level output voltage VOL(PG) 0.4 V VOUT < VIT(PG), IPG = -1 mA (current into device) 6
PG pin leakage current Ilkg(PG) 1 µA VOUT > VIT(PG), V(PG) = 6.5 V 6
SS pin charging current I(SS) 3.5 5.1 7.2 µA V(SS) = GND, VIN = 3.3 V 6
Thermal shutdown temperature Tsd 160 °C Shutdown, temperature increasing 6
Thermal reset temperature Tsd 140 °C Reset, temperature decreasing 6
Operating junction temperature TJ -40 125 °C 6
Input voltage (absolute max) IN -0.3 7 V IN, PG, EN pins 4
Voltage on SS, FB, SNS, OUT SS, FB, SNS, OUT -0.3 V Max VIN + 0.3 V or +7 V, whichever is smaller 4
Voltage on output setting pins 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, 1.6 V -0.3 V Max VOUT + 0.3 V 4
PG sink current PG 5 mA Sink current into IC 4
Operating virtual junction temperature TJ -55 160 °C 4
Storage temperature Tstg -55 150 °C 4
Supply voltage, recommended VIN 1.425 6.5 V Supply voltage 4
Output voltage, recommended VOUT 0.9 5 V Output voltage 4
Enable voltage, recommended VEN 0 6.5 V Enable voltage 4
Pullup voltage, recommended VPG 0 6.5 V Pullup voltage 4
Any-out voltage, recommended 0 V 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, 1.6 V pins; max VOUT 4
Output current, recommended IOUT 0 1 A Output current 4
Output capacitance, recommended COUT 4.7 200 µF For output capacitors larger than 47 µF a feedforward capacitor of at least 220 pF must be used 4
Feedforward capacitance, recommended CFF 0 100 nF Feedforward capacitance 4
Junction temperature, recommended TJ -40 125 °C Junction temperature range 4
Junction-to-ambient thermal resistance (RGT) RθJA 44.6 °C/W Junction-to-ambient, RGT (16 pins) 5
Junction-to-case (top) thermal resistance (RGT) RθJC(top) 54.3 °C/W Junction-to-case (top), RGT (16 pins) 5
Junction-to-board thermal resistance (RGT) RθJB 17.2 °C/W Junction-to-board, RGT (16 pins) 5
Junction-to-top characterization parameter (RGT) ψJT 1.1 °C/W Junction-to-top, RGT (16 pins) 5
Junction-to-board characterization parameter (RGT) ψJB 17.2 °C/W Junction-to-board, RGT (16 pins) 5
Junction-to-case (bottom) thermal resistance (RGT) RθJC(bot) 3.8 °C/W Junction-to-case (bottom), RGT (16 pins) 5
Dropout voltage V(DO) 140 mV VOUT ≤ 3.3 V, IOUT = 1 A, V(FB) = GND 6
Dropout voltage, high output V(DO) 350 mV 3.3 V < VOUT, IOUT = 1 A, V(FB) = GND 6
GND pin current, full load I(GND) 1.8 mA Full load, IOUT = 1 A 6
GND pin current, minimum load I(GND) 4 mA VIN = 6.5 V, VOUT(TARGET) = 0.9 V, IOUT = 25 mA 6
Shutdown ground current I(GND) 0.1 5 µA Shutdown, PG = (open), VIN = 6.5 V, VOUT(TARGET) = 0.9 V, V(EN) < 0.5 V 6
Line regulation ΔVO(ΔVI) 0.01 %/V IOUT = 25 mA 6
Load regulation ΔVO(ΔIO) 0.1 %/A 25 mA ≤ IOUT ≤ 1 A 6
Output noise voltage Vn 39.57 µVRMS BW = 100 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.2 V, IOUT = 1 A 6

CAD (KiCad official)

  • Symbol: TPS7A7100RGTT
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps7a7100rgtt-etched.step / tps7a7100rgtt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7a7100rgtt.step / tps7a7100rgtt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 32406be81dc0767e, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF