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TPS7A6950QDRQ1
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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+45@@ -0,0 +1,45 @@+# TPS7A6950QDRQ1++**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8++TPS7A6950QDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VIN | power_in | Input power-supply voltage; the unregulated input operates from 4 V to 40 V, with absolute maximum 45 V (withstands 45 V for 200 ms). |+| 2 | SI | input | Sense input to supervise input voltage, connected through an external voltage divider to VIN and GND; high-voltage I/O range 0 V to 40 V. |+| 3 | NC | unconnected | Not-connected pin with no internal connection. |+| 4 | CT | output | Reset-pulse delay adjustment; a capacitor from this pin to GND sets the PG reset delay, with CT pin voltage rated 0 V to 20 V (absolute maximum 25 V). |+| 5 | GND | power_in | Ground reference. |+| 6 | PG | output | Power-good open-drain output that must connect to VOUT via an external resistor, going logic high when VOUT is above the power-on-reset threshold; low-voltage I/O range 0 V to 5.5 V. |+| 7 | SO | output | Sense open-drain output that must connect to VOUT via an external resistor, going logic low when VSI falls below the sense-low threshold; low-voltage I/O range 0 V to 5.5 V. |+| 8 | VOUT | power_out | Regulated output voltage, 1.5 V to 5.5 V recommended operating range with absolute maximum 7 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-8 |+| Category | Power Management (PMIC) |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `TPS7A6950QDRQ1`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)+- 3D model files: `tps7a6950qdrq1-etched.step` / `tps7a6950qdrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7a6950qdrq1.step` / `tps7a6950qdrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps7a69-q1) (38 pp, sha256 `f851d4872d5fd0bc`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps7a6950qdrq1-datasheet.pdf)
page.jsonadded+200@@ -0,0 +1,200 @@+{+ "slug": "tps7a6950qdrq1",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "tps7a6950qdrq1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps7a6950qdrq1.kicad_sym",+ "tps7a6950qdrq1.kicad_mod",+ "tps7a6950qdrq1.glb",+ "tps7a6950qdrq1.step",+ "tps7a6950qdrq1.lbr",+ "docs/hero.png",+ "docs/tps7a6950qdrq1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tps7a6950qdrq1-hero.glb",+ "tps7a6950qdrq1-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPS7A6950QDRQ1",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-8",+ "pin_count": 8,+ "category": "Power Management (PMIC)",+ "subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps7a69-q1",+ "parts": {+ "symbol": "tps7a6950qdrq1.kicad_sym",+ "footprint": "tps7a6950qdrq1.kicad_mod",+ "model_3d": "tps7a6950qdrq1-hero.glb",+ "model_3d_plain": "tps7a6950qdrq1.glb",+ "model_3d_step": "tps7a6950qdrq1-etched.step",+ "model_3d_step_plain": "tps7a6950qdrq1.step",+ "lbr": "tps7a6950qdrq1.lbr"+ },+ "distributor_links": {+ "lcsc": "C2869567",+ "digikey": "296-37004-2-ND",+ "mouser": "595-TPS7A6950QDRQ1"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T00:01:49Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-37004-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS7A6950QDRQ1",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VIN",+ "type": "power_in",+ "description": "Input power-supply voltage; the unregulated input operates from 4 V to 40 V, with absolute maximum 45 V (withstands 45 V for 200 ms)."+ },+ {+ "number": "2",+ "name": "SI",+ "type": "input",+ "description": "Sense input to supervise input voltage, connected through an external voltage divider to VIN and GND; high-voltage I/O range 0 V to 40 V."+ },+ {+ "number": "3",+ "name": "NC",+ "type": "unconnected",+ "description": "Not-connected pin with no internal connection."+ },+ {+ "number": "4",+ "name": "CT",+ "type": "output",+ "description": "Reset-pulse delay adjustment; a capacitor from this pin to GND sets the PG reset delay, with CT pin voltage rated 0 V to 20 V (absolute maximum 25 V)."+ },+ {+ "number": "5",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "6",+ "name": "PG",+ "type": "output",+ "description": "Power-good open-drain output that must connect to VOUT via an external resistor, going logic high when VOUT is above the power-on-reset threshold; low-voltage I/O range 0 V to 5.5 V."+ },+ {+ "number": "7",+ "name": "SO",+ "type": "output",+ "description": "Sense open-drain output that must connect to VOUT via an external resistor, going logic low when VSI falls below the sense-low threshold; low-voltage I/O range 0 V to 5.5 V."+ },+ {+ "number": "8",+ "name": "VOUT",+ "type": "power_out",+ "description": "Regulated output voltage, 1.5 V to 5.5 V recommended operating range with absolute maximum 7 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The MPN TPS7A6950QDRQ1 is listed in the ordering addendum (page 24) as SOIC (D), 8 pins, so the SOIC; The SOIC column of the pin table has no entry for EN or FB/DNC (shown as '—'), and the thermal pad i; Pin types follow the datasheet's printed codes where they map cleanly. CT is printed as 'O' and is m"+ ],+ "pages_sent": 8,+ "cost_usd": 0.062,+ "at": "2026-10-08T00:01:32"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps7a69-q1",+ "pages": 38,+ "sha256": "f851d4872d5fd0bc",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps7a6950qdrq1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 4.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps7a6950qdrq1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 4.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "0c14f77a1c08c347e65c540e2b08097528fb7f8c8ea59bd1729420a96748a13b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}