component
TPS7A6933QDRQ1
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS7A6933QDRQ1
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8
TPS7A6933QDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input power-supply voltage for 4 V to 40 V operation. |
| 2 | SI | input | Sense input pin to supervise input voltage via external voltage divider to VIN and GND. |
| 3 | NC | unconnected | Not-connected pin with no internal connection. |
| 4 | CT | output | Reset-pulse delay adjustment pin; connect a capacitor from this pin to GND to control the PG reset delay. |
| 5 | GND | power_in | Ground reference. |
| 6 | PG | tri_state | Power good open-drain output that must connect to VOUT via an external resistor; logic high when VOUT exceeds the power-on-reset threshold. |
| 7 | SO | tri_state | Sense output open-drain pin that must connect to VOUT via an external resistor; logic low when sense input falls below the sense-low threshold. |
| 8 | VOUT | power_out | Regulated output voltage with 150 mA output current capability and 300 mV typical dropout at 150 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TPS7A6933QDRQ1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tps7a6933qdrq1-etched.step/tps7a6933qdrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a6933qdrq1.step/tps7a6933qdrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
f851d4872d5fd0bc, retrieved 2026-10-05, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS7A6933QDRQ1
**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8
TPS7A6933QDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input power-supply voltage for 4 V to 40 V operation. |
| 2 | SI | input | Sense input pin to supervise input voltage via external voltage divider to VIN and GND. |
| 3 | NC | unconnected | Not-connected pin with no internal connection. |
| 4 | CT | output | Reset-pulse delay adjustment pin; connect a capacitor from this pin to GND to control the PG reset delay. |
| 5 | GND | power_in | Ground reference. |
| 6 | PG | tri_state | Power good open-drain output that must connect to VOUT via an external resistor; logic high when VOUT exceeds the power-on-reset threshold. |
| 7 | SO | tri_state | Sense output open-drain pin that must connect to VOUT via an external resistor; logic low when sense input falls below the sense-low threshold. |
| 8 | VOUT | power_out | Regulated output voltage with 150 mA output current capability and 300 mV typical dropout at 150 mA. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `TPS7A6933QDRQ1`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `tps7a6933qdrq1-etched.step` / `tps7a6933qdrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7a6933qdrq1.step` / `tps7a6933qdrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps7a69-q1) (38 pp, sha256 `f851d4872d5fd0bc`, retrieved 2026-10-05, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps7a6933qdrq1-datasheet.pdf)