# TPS7A6650HQDGNRQ1

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · MSOP-8

TPS7A6650HQDGNRQ1 from Texas Instruments, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Vin | power_in | Input power-supply voltage with a recommended range of 4 V to 40 V, an absolute maximum of -0.3 V to 45 V, and a 45 V withstand for 200 ms. |
| 2 | EN | input | Enable pin: holding it below 0.4 V puts the device in standby, and it must be above 1.7 V to enable the regulator, with a recommended range of 0 V to 40 V. |
| 3 | NC | unconnected | Not-connected pin with no internal connection. |
| 4 | CT | output | Reset-pulse delay adjustment pin, connected through a capacitor to GND, with a recommended capacitor range of 100 pF to 100 nF and a voltage limit of 0 V to 20 V (absolute maximum 25 V). |
| 5 | GND | power_in | Ground reference for the device. |
| 6 | PG | output | Open-drain output-ready pin that must connect to Vout through an external resistor and is pulled low when Vout falls below threshold, with VOL of 0.4 V maximum at 0.5 mA and a recommended range of 0 V to 5.5 V. |
| 7 | NU | unconnected | Not-used pin; make no external connection. |
| 8 | Vout | power_out | Regulated 5 V fixed output with a recommended range of 1.5 V to 5.5 V, a 7 V absolute maximum, and up to 50 mA output current. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | MSOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Regulated output accuracy, IO = 1 mA, TJ = 25°C | V(Vout) | -1 |  | 1 | % | IO = 1 mA, TJ = 25°C | 5 |
| Regulated output accuracy, line and load | V(Vout) | -2 |  | 2 | % | V(Vin) = 6 V to 40 V, IO = 1 mA to 50 mA | 5 |
| Input voltage | V(Vin) | 5.5 |  | 40 | V | IO = 1 mA | 4 |
| Quiescent current | I(q) |  | 12 | 22 | µA | V(Vin) = 5.5 V to 40 V, EN = ON, IO = 0.2 mA | 4 |
| Output current | IO | 0 |  | 50 | mA | V(Vout) in regulation | 5 |
| Output current limit | I(lreg-CL) | 500 |  | 800 | mA | V(Vout) short to ground | 5 |
| Dropout voltage | V(dropout) |  | 130 | 240 | mV | V(dropout) = V(Vin) – V(Vout), IOUT = 50 mA | 5 |
| Power-on-reset threshold | V(TH-POR) | 89.6 | 91.6 | 93.6 | % of Vout | V(Vout) increasing | 5 |
| Reset output low voltage | VOL |  |  | 0.4 | V | IOL = 0.5 mA | 5 |
| Logic input low level (EN) | VIL | 0 |  | 0.4 | V |  | 4 |
| Reset deglitch time | t(Deglitch) | 20 | 250 |  | µs |  | 5 |
| Power-on-reset delay | t(POR) | 50 | 100 | 180 | ms | Capacitance C = 100 nF | 5 |
| Power-on-reset delay, no capacitor on CT | t(POR-fixed) | 100 | 290 | 650 | µs | No capacitor on pin | 5 |
| Operating junction temperature range | TJ | -40 |  | 160 | °C |  | 5 |
| Input voltage (absolute maximum, unregulated) | Vin | -0.3 |  | 45 | V | Unregulated input; withstand 45 V for 200 ms | 3 |
| EN pin voltage (absolute maximum) | EN | -0.3 |  | 45 | V |  | 3 |
| Regulated output voltage (absolute maximum) | Vout | -0.3 |  | 7 | V | Regulated output | 3 |
| CT pin voltage (absolute maximum) | CT | -0.3 |  | 25 | V |  | 3 |
| PG pin voltage (absolute maximum) | PG | -0.3 |  |  | V | Printed maximum is Vout (not a numeric value) | 3 |
| Operating junction temperature range (absolute maximum) | TJ | -40 |  | 160 | °C | Operating junction temperature range | 3 |
| Storage temperature range | Tstg | -65 |  | 160 | °C |  | 3 |
| Unregulated input voltage (recommended) | Vin | 4 |  | 40 | V | Unregulated input | 4 |
| EN pin voltage (recommended) | EN | 0 |  | 40 | V |  | 4 |
| CT pin voltage (recommended) | CT | 0 |  | 20 | V |  | 4 |
| Regulated output voltage (recommended) | Vout | 1.5 |  | 5.5 | V |  | 4 |
| PG low voltage (I/O, recommended) | PG | 0 |  | 5.5 | V | Low voltage (I/O) | 4 |
| Operating ambient temperature | TA | -40 |  | 150 | °C |  | 4 |
| Human body model ESD | V(ESD) HBM | -4000 |  | 4000 | V | Per AEC Q100-002 | 4 |
| Charged device model ESD | V(ESD) CDM | -1000 |  | 1000 | V | All pins, per AEC Q100-011 | 4 |
| Input sleep current | I(Sleep) |  | 4 |  | µA | No load current and EN = OFF | 4 |
| EN pin current | I(EN) |  | 1 |  | µA | V(EN) = 40 V | 4 |
| Undervoltage detection | V(VinUVLO) |  | 2.6 |  | V | Ramp V(Vin) down until output turns OFF | 4 |
| Undervoltage hysteresis | V(UVLOhys) |  | 1 |  | V |  | 4 |
| Logic input high level (EN) | VIH |  | 1.7 |  | V |  | 4 |
| Line regulation | V(line-reg) |  | 5 |  | mV | V(Vin) = 5.5 V to 40 V, IO = 50 mA | 5 |
| Load regulation | V(load-reg) |  | 20 |  | mV | IO = 1 mA to 50 mA | 5 |
| Power supply ripple rejection at 100 Hz | PSRR |  | 60 |  | dB | V(Vin) = 12 V, IL = 10 mA, output capacitance = 2.2 µF, frequency = 100 Hz | 5 |
| Power supply ripple rejection at 100 kHz | PSRR |  | 40 |  | dB | V(Vin) = 12 V, IL = 10 mA, output capacitance = 2.2 µF, frequency = 100 kHz | 5 |
| Power-on-reset hysteresis | V(Thres) |  | 2 |  | % of Vout |  | 5 |
| Reset leakage current | Ilkg |  | 1 |  | µA | Reset pulled Vout through 10-kΩ resistor | 5 |
| Delay-capacitor charging current | I(Chg) |  | 1.4 |  | µA | V(CT) = 0 V | 5 |
| Threshold to release PG high | V(th) |  | 1 |  | V |  | 5 |
| Junction shutdown temperature | T(shutdown) |  | 175 |  | °C |  | 5 |
| Hysteresis of thermal shutdown | T(hyst) |  | 20 |  | °C |  | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 63.4 |  | °C/W | DGN (HVSSOP) 8-pin package | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 53 |  | °C/W | DGN (HVSSOP) 8-pin package | 4 |
| Junction-to-board thermal resistance | RθJB |  | 37.4 |  | °C/W | DGN (HVSSOP) 8-pin package | 4 |
| Junction-to-top characterization parameter | ψJT |  | 3.7 |  | °C/W | DGN (HVSSOP) 8-pin package | 4 |
| Junction-to-board characterization parameter | ψJB |  | 37.1 |  | °C/W | DGN (HVSSOP) 8-pin package | 4 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 13.5 |  | °C/W | DGN (HVSSOP) 8-pin package | 4 |

## CAD (KiCad official)

- Symbol: `TPS7A6650HQDGNRQ1`
- Footprint: `Package_SO:MSOP-8_3x3mm_P0.65mm`
- 3D model: MSOP-8 (KiCad packages3D, STEP)
- 3D model files: `tps7a6650hqdgnrq1-etched.step` / `tps7a6650hqdgnrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7a6650hqdgnrq1.step` / `tps7a6650hqdgnrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps7a6650h-q1) (20 pp, sha256 `1abb202ad700afb3`, retrieved 2026-10-11, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps7a6650hqdgnrq1-datasheet.pdf)