TPS7A5701RTER

TEXAS INSTRUMENTS · Global Sourcing Parts · WQFN-16(3x3)

TPS7A5701RTER from TEXAS INSTRUMENTS, in a WQFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN	power_in	Input supply pin; the recommended VIN range is 0.7 V to 6 V and the absolute maximum is 6.5 V (page 5 limit for IN/PG/EN/CP_EN).
2	IN	power_in	Input supply pin; the recommended VIN range is 0.7 V to 6 V and the absolute maximum is 6.5 V (page 5 limit for IN/PG/EN/CP_EN).
3	IN	power_in	Input supply pin; the recommended VIN range is 0.7 V to 6 V and the absolute maximum is 6.5 V (page 5 limit for IN/PG/EN/CP_EN).
4	IN	power_in	Input supply pin; the recommended VIN range is 0.7 V to 6 V and the absolute maximum is 6.5 V (page 5 limit for IN/PG/EN/CP_EN).
5	BIAS	power_in	Bias supply pin with a recommended range of 3 V to 11 V and an absolute maximum of 11.2 V; it is needed when the charge pump is disabled or VIN is below 1.1 V.
6	GND	power_in	Ground pin; the exposed thermal pad should also be tied to GND for best thermal performance.
7	REF	bidirectional	Reference pin where the RREF resistor to GND sets the output voltage via VOUT = IREF × RREF, with a recommended VREF range of 0.5 V to 5.3 V and an absolute maximum of 6 V.
8	NR/SS	bidirectional	Noise-reduction and soft-start pin where CNR/SS (typically 4.7 µF, range 0.1 µF to 10 µF) sets the startup ramp and filters reference noise, with an absolute maximum of 6 V.
9	OUT	power_out	Regulated output pin, rated for output currents from 0 A to 5 A and limited internally, with an absolute maximum of VIN + 0.3 V or 6.0 V, whichever is smaller.
10	OUT	power_out	Regulated output pin, rated for output currents from 0 A to 5 A and limited internally, with an absolute maximum of VIN + 0.3 V or 6.0 V, whichever is smaller.
11	OUT	power_out	Regulated output pin, rated for output currents from 0 A to 5 A and limited internally, with an absolute maximum of VIN + 0.3 V or 6.0 V, whichever is smaller.
12	OUT	power_out	Regulated output pin, rated for output currents from 0 A to 5 A and limited internally, with an absolute maximum of VIN + 0.3 V or 6.0 V, whichever is smaller.
13	SNS	input	Output sense pin that must be connected to OUT for unity-gain operation and load sensing, with an absolute maximum of 6 V.
14	PG	output	Open-drain power-good output that asserts when VOUT is above 90% of its set value (2% hysteresis), requires a 10 kΩ to 100 kΩ pull-up, can sink up to 5 mA, and has an absolute maximum of 6.5 V.
15	CP_EN	input	Charge-pump enable pin that must be tied to IN, BIAS, or GND rather than driven by digital I/O, with an absolute maximum of 6.5 V and a ±5 µA pin current.
16	EN	input	Precision enable pin with an absolute maximum of 6.5 V, a rising threshold of about 0.65 V with 40 mV hysteresis, and no internal pull-down, so it should not be left floating.
17	GND	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	TEXAS INSTRUMENTS
Package	WQFN-16(3x3)
Category	Global Sourcing Parts
Pins	17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input supply voltage range	VIN	0.7		6	V		6
Reference voltage range	VREF	0.5		5.3	V		6
Output voltage range	VOUT	0.5		5.2	V		6
Bias voltage range	VBIAS	3		11	V		6
Output current	IOUT	0		5	A		6
Input capacitor	CIN	4.7	10	1000	µF		6
Output capacitor	COUT	22	22	3000	µF	Footnote 1: minimum 15 µF effective output capacitance required for stability	6
Output capacitor ESR	COUT_ESL	2		20	mΩ		6
Total impedance ESL	ZOUT_ESL	0.2		1	nH		6
BIAS pin capacitor	CBIAS	0	1	100	µF		6
Noise reduction capacitor	CNR/SS	0.1	4.7	10	µF		6
Power-good pull-up resistor	RPG	10		100	kΩ		6
Junction temperature	TJ	-40		125	°C		6
VUVLO(IN) input UVLO with BIAS	VUVLO(IN)	0.67		0.7	V	VIN rising, VCP_EN = 1.8V (3V ≤ VBIAS ≤ 11V) and VCP_EN = 0V (VOUT + 3.2V ≤ VBIAS ≤ 11V)	7
VUVLO(IN) input UVLO without BIAS	VUVLO(IN)	1.07		1.1	V	VIN rising, VCP_EN = 1.8V	7
VUVLO(BIAS) vs VREF	VUVLO(BIAS), VREF	2.1		2.95	V	VBIAS rising, VCP_EN = 0V, 0.5V ≤ VREF ≤ 5.2V	7
VUVLO(BIAS) with charge pump	VUVLO(BIAS)	2.8		2.95	V	VBIAS rising, VCP_EN = 1.8V, 0.7V ≤ VIN < 1.1V	7
VOUT output voltage accuracy	VOUT	-1		1	%	0.5V ≤ VOUT ≤ 5.2V, 0A ≤ IOUT ≤ 5A, VCP_EN = 0V, VOUT + 3.2V ≤ VBIAS ≤ 11V, 0.7V ≤ VIN ≤ 6V	7
Output offset voltage (VNR/SS - VOUT)	VOS	-1		1	mV	VIN = 0.7V, VOUT = 0.5V, IOUT = 0A, VCP_EN = 1.8V, 3V ≤ VBIAS ≤ 11V; VCP_EN = 0V, VOUT + 3.2V ≤ VBIAS ≤ 11V	7
Output offset voltage (VNR/SS - VOUT)	VOS	-2		2	mV	0.7V ≤ VIN ≤ 6V, 0.5V ≤ VOUT ≤ 5.2V, VCP_EN = 1.8V, 3V ≤ VBIAS ≤ 11V, 0A ≤ IOUT ≤ 5A	7
Dropout voltage	VDO		75	110	mV	1.1V ≤ VIN ≤ 5.3V, IOUT = 5A, VCP_EN = 1.8V, -40°C ≤ TJ ≤ +125°C	8
Dropout voltage	VDO			100	mV	1.1V ≤ VIN ≤ 5.3V, IOUT = 5A, VCP_EN = 1.8V, -40°C ≤ TJ ≤ +85°C	8
Output current limit	ILIM	5.2	6	6.7	A	VOUT forced to 0.9 × VOUT(NOM), VOUT(NOM) = 5.2V, VIN = VOUT(NOM) + 400mV, VCP_EN = 0V, VBIAS = VOUT + 3.2V	8
BIAS pin current	IBIAS	0.5	1.5	2.5	mA	VIN = 6V, IOUT = 0A, VCP_EN = 0V, VBIAS = VOUT + 3.2V, VOUT = 5.2V	8
BIAS pin current	IBIAS	8	11	15	mA	VIN = 0.7V, IOUT = 5A, VOUT = 0.5V, VCP_EN = 1.8V, 3.0V ≤ VBIAS ≤ 11V	8
GND pin current	IGND	3.5	5	6.5	mA	VIN = 6V, IOUT = 0A, VCP_EN = 0V, VBIAS = VOUT + 3.2V, VOUT = 5.2V	8
GND pin current	IGND	12	17.5	24	mA	VIN = 1.1V, IOUT = 5A, VOUT = 0.5V, VCP_EN = 1.8V, VBIAS = 0V	8
GND pin current	IGND	11	16.5	23	mA	VIN = 0.7V, IOUT = 5A, VOUT = 0.5V, VCP_EN = 1.8V, 3V ≤ VBIAS ≤ 11V	8
GND pin current	IGND	5	7	9	mA	VIN = 0.7V, IOUT = 5A, VOUT = 0.5V, VCP_EN = 0V, VOUT + 3.2V ≤ VBIAS ≤ 11V	8
Shutdown GND pin current	ISDN		100	300	µA	PG open, VIN = 6V, VEN = 0.4V, VCP_EN = 1.8V, VBIAS = 0V	8
Shutdown GND pin current	ISDN		150	450	µA	PG open, VIN = 6V, VEN = 0.4V, VCP_EN = 0.4V, VBIAS = 11V	8
EN pin current	IEN	-5		5	µA	VIN = 6V, 0V ≤ VEN ≤ 6V, VCP_EN = 1.8V, VBIAS = 0V	8
EN rising threshold (turn-on)	VIH(EN)	0.62	0.65	0.68	V	VIN = 1.1V (VCP_EN = 1.8V) or VBIAS ≥ 3V (VCP_EN = 0V)	8
CP_EN pin current	ICP_EN	-5		5	µA	VIN = 6.0V, 0V ≤ VCP_EN ≤ 6V	8
CP_EN rising threshold (turn-on)	VIH(CP_EN)	0.57	0.6	0.63	V	1.1V ≤ VIN ≤ 6V, VEN = 1.8V, VBIAS = 0V; or 0.7V ≤ VIN ≤ 1.1V, VEN = 1.8V, VBIAS = 3V	8
Thermal resistance junction-to-ambient (RθJA)	RθJA		40.3		°C/W	JEDEC standard (2s2p) board, note 2	6
Thermal resistance junction-to-ambient (RθJA)	RθJA		21.9		°C/W	EVM board, note 3	6
Thermal resistance junction-to-case top (RθJC(top))	RθJC(top)		37.2		°C/W	JEDEC standard (2s2p) board, note 2	6
Thermal resistance junction-to-board (RθJB)	RθJB		14.5		°C/W	JEDEC standard (2s2p) board, note 2	6
Thermal resistance junction-to-case bottom (RθJC(bot))	RθJC(bot)		1.9		°C/W	JEDEC standard (2s2p) board, note 2	6
NR/SS fast-start charge current	INR/SS		0.2		mA	VNR/SS = GND, VIN = 1.1V	7
REF pin current	IREF		50		µA	VIN = 1.1V, VCP_EN = 1.8V, VOUT = 0.5V, ILOAD = 0A, VBIAS = 0V	7
Input UVLO hysteresis with BIAS	VHYS(UVLO_IN)		50		mV	VCP_EN = 1.8V (3V ≤ VBIAS ≤ 11V) and VCP_EN = 0V (VOUT + 3.2V ≤ VBIAS ≤ 11V)	7
Input UVLO hysteresis without BIAS	VHYS(UVLO_IN)		50		mV	VCP_EN = 1.8V	7
BIAS UVLO hysteresis vs VREF	VHYS(UVLO_BIAS - REF)		240		mV	VCP_EN = 0V, 0.5V ≤ VREF ≤ 5.2V	7
BIAS UVLO hysteresis with charge pump	VHYS(UVLO_BIAS)		115		mV	VCP_EN = 1.8V, 0.7V ≤ VIN < 1.1V	7
Load regulation	ΔVOS(ΔIOUT)		5		µV/A	VIN = 0.7V, VOUT = 0.5V, VCP_EN = 0V, 0A ≤ IOUT ≤ 5A, VOUT + 3.2V ≤ VBIAS ≤ 11V	8
Load regulation	ΔVOS(ΔIOUT)		175		µV/A	VOUT = 5.2V, VCP_EN = 1.8V, 0A ≤ IOUT ≤ 5A, VBIAS = 0V	8
Short-circuit current limit	ISC		4		A	RLOAD = 10mΩ (foldback operating condition)	8
GND pin current	IGND		16.5		mA	VIN = 5.6V, IOUT = 5A, VOUT = 5.2V, VCP_EN = 1.8V, VBIAS = 0V	8
EN pin hysteresis	VHYS(EN)		40		mV	VIN = 1.1V (VCP_EN = 1.8V) or VBIAS ≥ 3V (VCP_EN = 0V)	7
CP_EN threshold hysteresis	VHYS(CP_EN)		56		mV	1.1V ≤ VIN ≤ 6V, VEN = 1.8V, VBIAS = 0V; or 0.7V ≤ VIN ≤ 1.1V, VEN = 1.8V, VBIAS = 3V	8

CAD (KiCad official)

Symbol: TPS7A5701RTER
Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
3D model: WQFN-16(3x3) (KiCad packages3D, STEP)
3D model files: tps7a5701rter-etched.step / tps7a5701rter-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7a5701rter.step / tps7a5701rter.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: TEXAS INSTRUMENTS datasheet (102 pp, sha256 4864901f70386e95, retrieved 2026-10-21, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# TPS7A5701RTER

**TEXAS INSTRUMENTS** · Global Sourcing Parts · WQFN-16(3x3)

TPS7A5701RTER from TEXAS INSTRUMENTS, in a WQFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input supply pin; the recommended VIN range is 0.7 V to 6 V and the absolute maximum is 6.5 V (page 5 limit for IN/PG/EN/CP_EN). |
| 2 | IN | power_in | Input supply pin; the recommended VIN range is 0.7 V to 6 V and the absolute maximum is 6.5 V (page 5 limit for IN/PG/EN/CP_EN). |
| 3 | IN | power_in | Input supply pin; the recommended VIN range is 0.7 V to 6 V and the absolute maximum is 6.5 V (page 5 limit for IN/PG/EN/CP_EN). |
| 4 | IN | power_in | Input supply pin; the recommended VIN range is 0.7 V to 6 V and the absolute maximum is 6.5 V (page 5 limit for IN/PG/EN/CP_EN). |
| 5 | BIAS | power_in | Bias supply pin with a recommended range of 3 V to 11 V and an absolute maximum of 11.2 V; it is needed when the charge pump is disabled or VIN is below 1.1 V. |
| 6 | GND | power_in | Ground pin; the exposed thermal pad should also be tied to GND for best thermal performance. |
| 7 | REF | bidirectional | Reference pin where the RREF resistor to GND sets the output voltage via VOUT = IREF × RREF, with a recommended VREF range of 0.5 V to 5.3 V and an absolute maximum of 6 V. |
| 8 | NR/SS | bidirectional | Noise-reduction and soft-start pin where CNR/SS (typically 4.7 µF, range 0.1 µF to 10 µF) sets the startup ramp and filters reference noise, with an absolute maximum of 6 V. |
| 9 | OUT | power_out | Regulated output pin, rated for output currents from 0 A to 5 A and limited internally, with an absolute maximum of VIN + 0.3 V or 6.0 V, whichever is smaller. |
| 10 | OUT | power_out | Regulated output pin, rated for output currents from 0 A to 5 A and limited internally, with an absolute maximum of VIN + 0.3 V or 6.0 V, whichever is smaller. |
| 11 | OUT | power_out | Regulated output pin, rated for output currents from 0 A to 5 A and limited internally, with an absolute maximum of VIN + 0.3 V or 6.0 V, whichever is smaller. |
| 12 | OUT | power_out | Regulated output pin, rated for output currents from 0 A to 5 A and limited internally, with an absolute maximum of VIN + 0.3 V or 6.0 V, whichever is smaller. |
| 13 | SNS | input | Output sense pin that must be connected to OUT for unity-gain operation and load sensing, with an absolute maximum of 6 V. |
| 14 | PG | output | Open-drain power-good output that asserts when VOUT is above 90% of its set value (2% hysteresis), requires a 10 kΩ to 100 kΩ pull-up, can sink up to 5 mA, and has an absolute maximum of 6.5 V. |
| 15 | CP_EN | input | Charge-pump enable pin that must be tied to IN, BIAS, or GND rather than driven by digital I/O, with an absolute maximum of 6.5 V and a ±5 µA pin current. |
| 16 | EN | input | Precision enable pin with an absolute maximum of 6.5 V, a rising threshold of about 0.65 V with 40 mV hysteresis, and no internal pull-down, so it should not be left floating. |
| 17 | GND | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | TEXAS INSTRUMENTS |
| Package | WQFN-16(3x3) |
| Category | Global Sourcing Parts |
| Pins | 17 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply voltage range | VIN | 0.7 |  | 6 | V |  | 6 |
| Reference voltage range | VREF | 0.5 |  | 5.3 | V |  | 6 |
| Output voltage range | VOUT | 0.5 |  | 5.2 | V |  | 6 |
| Bias voltage range | VBIAS | 3 |  | 11 | V |  | 6 |
| Output current | IOUT | 0 |  | 5 | A |  | 6 |
| Input capacitor | CIN | 4.7 | 10 | 1000 | µF |  | 6 |
| Output capacitor | COUT | 22 | 22 | 3000 | µF | Footnote 1: minimum 15 µF effective output capacitance required for stability | 6 |
| Output capacitor ESR | COUT_ESL | 2 |  | 20 | mΩ |  | 6 |
| Total impedance ESL | ZOUT_ESL | 0.2 |  | 1 | nH |  | 6 |
| BIAS pin capacitor | CBIAS | 0 | 1 | 100 | µF |  | 6 |
| Noise reduction capacitor | CNR/SS | 0.1 | 4.7 | 10 | µF |  | 6 |
| Power-good pull-up resistor | RPG | 10 |  | 100 | kΩ |  | 6 |
| Junction temperature | TJ | -40 |  | 125 | °C |  | 6 |
| VUVLO(IN) input UVLO with BIAS | VUVLO(IN) | 0.67 |  | 0.7 | V | VIN rising, VCP_EN = 1.8V (3V ≤ VBIAS ≤ 11V) and VCP_EN = 0V (VOUT + 3.2V ≤ VBIAS ≤ 11V) | 7 |
| VUVLO(IN) input UVLO without BIAS | VUVLO(IN) | 1.07 |  | 1.1 | V | VIN rising, VCP_EN = 1.8V | 7 |
| VUVLO(BIAS) vs VREF | VUVLO(BIAS), VREF | 2.1 |  | 2.95 | V | VBIAS rising, VCP_EN = 0V, 0.5V ≤ VREF ≤ 5.2V | 7 |
| VUVLO(BIAS) with charge pump | VUVLO(BIAS) | 2.8 |  | 2.95 | V | VBIAS rising, VCP_EN = 1.8V, 0.7V ≤ VIN < 1.1V | 7 |
| VOUT output voltage accuracy | VOUT | -1 |  | 1 | % | 0.5V ≤ VOUT ≤ 5.2V, 0A ≤ IOUT ≤ 5A, VCP_EN = 0V, VOUT + 3.2V ≤ VBIAS ≤ 11V, 0.7V ≤ VIN ≤ 6V | 7 |
| Output offset voltage (VNR/SS - VOUT) | VOS | -1 |  | 1 | mV | VIN = 0.7V, VOUT = 0.5V, IOUT = 0A, VCP_EN = 1.8V, 3V ≤ VBIAS ≤ 11V; VCP_EN = 0V, VOUT + 3.2V ≤ VBIAS ≤ 11V | 7 |
| Output offset voltage (VNR/SS - VOUT) | VOS | -2 |  | 2 | mV | 0.7V ≤ VIN ≤ 6V, 0.5V ≤ VOUT ≤ 5.2V, VCP_EN = 1.8V, 3V ≤ VBIAS ≤ 11V, 0A ≤ IOUT ≤ 5A | 7 |
| Dropout voltage | VDO |  | 75 | 110 | mV | 1.1V ≤ VIN ≤ 5.3V, IOUT = 5A, VCP_EN = 1.8V, -40°C ≤ TJ ≤ +125°C | 8 |
| Dropout voltage | VDO |  |  | 100 | mV | 1.1V ≤ VIN ≤ 5.3V, IOUT = 5A, VCP_EN = 1.8V, -40°C ≤ TJ ≤ +85°C | 8 |
| Output current limit | ILIM | 5.2 | 6 | 6.7 | A | VOUT forced to 0.9 × VOUT(NOM), VOUT(NOM) = 5.2V, VIN = VOUT(NOM) + 400mV, VCP_EN = 0V, VBIAS = VOUT + 3.2V | 8 |
| BIAS pin current | IBIAS | 0.5 | 1.5 | 2.5 | mA | VIN = 6V, IOUT = 0A, VCP_EN = 0V, VBIAS = VOUT + 3.2V, VOUT = 5.2V | 8 |
| BIAS pin current | IBIAS | 8 | 11 | 15 | mA | VIN = 0.7V, IOUT = 5A, VOUT = 0.5V, VCP_EN = 1.8V, 3.0V ≤ VBIAS ≤ 11V | 8 |
| GND pin current | IGND | 3.5 | 5 | 6.5 | mA | VIN = 6V, IOUT = 0A, VCP_EN = 0V, VBIAS = VOUT + 3.2V, VOUT = 5.2V | 8 |
| GND pin current | IGND | 12 | 17.5 | 24 | mA | VIN = 1.1V, IOUT = 5A, VOUT = 0.5V, VCP_EN = 1.8V, VBIAS = 0V | 8 |
| GND pin current | IGND | 11 | 16.5 | 23 | mA | VIN = 0.7V, IOUT = 5A, VOUT = 0.5V, VCP_EN = 1.8V, 3V ≤ VBIAS ≤ 11V | 8 |
| GND pin current | IGND | 5 | 7 | 9 | mA | VIN = 0.7V, IOUT = 5A, VOUT = 0.5V, VCP_EN = 0V, VOUT + 3.2V ≤ VBIAS ≤ 11V | 8 |
| Shutdown GND pin current | ISDN |  | 100 | 300 | µA | PG open, VIN = 6V, VEN = 0.4V, VCP_EN = 1.8V, VBIAS = 0V | 8 |
| Shutdown GND pin current | ISDN |  | 150 | 450 | µA | PG open, VIN = 6V, VEN = 0.4V, VCP_EN = 0.4V, VBIAS = 11V | 8 |
| EN pin current | IEN | -5 |  | 5 | µA | VIN = 6V, 0V ≤ VEN ≤ 6V, VCP_EN = 1.8V, VBIAS = 0V | 8 |
| EN rising threshold (turn-on) | VIH(EN) | 0.62 | 0.65 | 0.68 | V | VIN = 1.1V (VCP_EN = 1.8V) or VBIAS ≥ 3V (VCP_EN = 0V) | 8 |
| CP_EN pin current | ICP_EN | -5 |  | 5 | µA | VIN = 6.0V, 0V ≤ VCP_EN ≤ 6V | 8 |
| CP_EN rising threshold (turn-on) | VIH(CP_EN) | 0.57 | 0.6 | 0.63 | V | 1.1V ≤ VIN ≤ 6V, VEN = 1.8V, VBIAS = 0V; or 0.7V ≤ VIN ≤ 1.1V, VEN = 1.8V, VBIAS = 3V | 8 |
| Thermal resistance junction-to-ambient (RθJA) | RθJA |  | 40.3 |  | °C/W | JEDEC standard (2s2p) board, note 2 | 6 |
| Thermal resistance junction-to-ambient (RθJA) | RθJA |  | 21.9 |  | °C/W | EVM board, note 3 | 6 |
| Thermal resistance junction-to-case top (RθJC(top)) | RθJC(top) |  | 37.2 |  | °C/W | JEDEC standard (2s2p) board, note 2 | 6 |
| Thermal resistance junction-to-board (RθJB) | RθJB |  | 14.5 |  | °C/W | JEDEC standard (2s2p) board, note 2 | 6 |
| Thermal resistance junction-to-case bottom (RθJC(bot)) | RθJC(bot) |  | 1.9 |  | °C/W | JEDEC standard (2s2p) board, note 2 | 6 |
| NR/SS fast-start charge current | INR/SS |  | 0.2 |  | mA | VNR/SS = GND, VIN = 1.1V | 7 |
| REF pin current | IREF |  | 50 |  | µA | VIN = 1.1V, VCP_EN = 1.8V, VOUT = 0.5V, ILOAD = 0A, VBIAS = 0V | 7 |
| Input UVLO hysteresis with BIAS | VHYS(UVLO_IN) |  | 50 |  | mV | VCP_EN = 1.8V (3V ≤ VBIAS ≤ 11V) and VCP_EN = 0V (VOUT + 3.2V ≤ VBIAS ≤ 11V) | 7 |
| Input UVLO hysteresis without BIAS | VHYS(UVLO_IN) |  | 50 |  | mV | VCP_EN = 1.8V | 7 |
| BIAS UVLO hysteresis vs VREF | VHYS(UVLO_BIAS - REF) |  | 240 |  | mV | VCP_EN = 0V, 0.5V ≤ VREF ≤ 5.2V | 7 |
| BIAS UVLO hysteresis with charge pump | VHYS(UVLO_BIAS) |  | 115 |  | mV | VCP_EN = 1.8V, 0.7V ≤ VIN < 1.1V | 7 |
| Load regulation | ΔVOS(ΔIOUT) |  | 5 |  | µV/A | VIN = 0.7V, VOUT = 0.5V, VCP_EN = 0V, 0A ≤ IOUT ≤ 5A, VOUT + 3.2V ≤ VBIAS ≤ 11V | 8 |
| Load regulation | ΔVOS(ΔIOUT) |  | 175 |  | µV/A | VOUT = 5.2V, VCP_EN = 1.8V, 0A ≤ IOUT ≤ 5A, VBIAS = 0V | 8 |
| Short-circuit current limit | ISC |  | 4 |  | A | RLOAD = 10mΩ (foldback operating condition) | 8 |
| GND pin current | IGND |  | 16.5 |  | mA | VIN = 5.6V, IOUT = 5A, VOUT = 5.2V, VCP_EN = 1.8V, VBIAS = 0V | 8 |
| EN pin hysteresis | VHYS(EN) |  | 40 |  | mV | VIN = 1.1V (VCP_EN = 1.8V) or VBIAS ≥ 3V (VCP_EN = 0V) | 7 |
| CP_EN threshold hysteresis | VHYS(CP_EN) |  | 56 |  | mV | 1.1V ≤ VIN ≤ 6V, VEN = 1.8V, VBIAS = 0V; or 0.7V ≤ VIN ≤ 1.1V, VEN = 1.8V, VBIAS = 3V | 8 |

## CAD (KiCad official)

- Symbol: `TPS7A5701RTER`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: WQFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files: `tps7a5701rter-etched.step` / `tps7a5701rter-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7a5701rter.step` / `tps7a5701rter.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [TEXAS INSTRUMENTS datasheet](https://www.ti.com/cn/lit/gpn/tps7a57) (102 pp, sha256 `4864901f70386e95`, retrieved 2026-10-21, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps7a5701rter-datasheet.pdf)