# TPS7A4901DRBR

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SON-8-EP(3x3)

TPS7A4901DRBR from Texas Instruments, in a SON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulator output; a capacitor of at least 2.2 µF must be tied from this pin to ground to ensure stability. |
| 2 | FB | input | Input to the error amplifier that sets the output voltage of the device. |
| 3 | NC | unconnected | Not internally connected; it can be left open or tied to GND. |
| 4 | GND | power_in | Ground reference pin. |
| 5 | EN | input | Enable pin: VEN ≥ VEN(high) enables the regulator and VEN ≤ VEN(low) disables it; it can be connected to IN if unused, and VEN must not exceed VIN. |
| 6 | NR/SS | passive | Noise-reduction pin where an external capacitor bypasses band-gap noise and sets the soft-start time. |
| 7 | DNC | unconnected | Do not connect; do not route this pin to any electrical net, not even GND or IN. |
| 8 | IN | power_in | Input supply; recommended VIN range is 3 V to 35 V (absolute maximum 36 V to GND). |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SON-8-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 3 |  | 35 | V |  | 6 |
| Internal reference | VREF | 1.176 | 1.188 | 1.212 | V | TJ = 25°C, VNR/SS = VREF | 6 |
| Output voltage range | VOUT |  |  | 33 | V | VIN ≥ VOUT(nom) + 1 V | 6 |
| Nominal accuracy |  | -1.5 |  | 1.5 | %VOUT | TJ = 25°C, VIN = VOUT(nom) + 0.5 V | 6 |
| Overall accuracy |  | -2.5 |  | 2.5 | %VOUT | VOUT(nom) + 1 V ≤ VIN ≤ 35 V, 1 mA ≤ IOUT ≤ 150 mA | 6 |
| Dropout voltage | VDO |  | 333 | 600 | mV | VIN = 95% VOUT(nom), IOUT = 150 mA | 6 |
| Current limit | ILIM | 220 | 309 | 500 | mA | VOUT = 90% VOUT(nom) | 6 |
| Ground current | IGND |  | 49 | 100 | μA | IOUT = 0 mA | 6 |
| Shutdown supply current | ISHDN |  | 0.8 | 3 | μA | VEN = 0.4 V | 6 |
| Feedback current | IFB |  | 3 | 100 | nA |  | 6 |
| Enable current | IEN |  | 0.02 | 1 | μA | VEN = VIN = VOUT(nom) + 1 V | 6 |
| Enable current | IEN |  | 0.2 | 1 | μA | VEN = VIN = 35 V | 6 |
| Enable high-level voltage | VEN(high) | 2.1 |  |  | V |  | 6 |
| Enable low-level voltage | VEN(low) | 0 |  | 0.4 | V |  | 6 |
| Input supply voltage | VIN | 3 |  | 35 | V |  | 5 |
| Enable supply voltage | VEN | 0 |  |  | V |  | 5 |
| Output voltage | VOUT |  |  | 33 | V |  | 5 |
| Output current | IOUT | 0 |  | 150 | mA |  | 5 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 5 |
| Input capacitor | CIN | 2.2 |  | 10 | µF |  | 5 |
| Output capacitor | COUT | 2.2 |  | 10 | µF |  | 5 |
| Noise reduction capacitor | CNR | 0 |  | 10 | nF |  | 5 |
| Feed-forward capacitor | CFF | 0 |  | 10 | nF |  | 5 |
| IN pin to GND pin | VIN | -0.3 |  | 36 | V |  | 5 |
| OUT pin to GND pin | VOUT | -0.3 |  | 33 | V |  | 5 |
| OUT pin to IN pin | VOUT-VIN | -36 |  | 0.3 | V |  | 5 |
| FB pin to GND pin | VFB | -0.3 |  | 2 | V |  | 5 |
| FB pin to IN pin | VFB-VIN | -36 |  | 0.3 | V |  | 5 |
| EN pin to IN pin | VEN-VIN | -36 |  | 0.3 | V |  | 5 |
| EN pin to GND pin | VEN | -0.3 |  | 36 | V |  | 5 |
| NR/SS pin to IN pin | VNR/SS-VIN | -36 |  | 0.3 | V |  | 5 |
| NR/SS pin to GND pin | VNR/SS | -0.3 |  | 2 | V |  | 5 |
| Operating virtual junction temperature | TJ | -40 |  | 125 | °C |  | 5 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 47.7 |  | °C/W | DRB (VSON-8) package | 6 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 55.3 |  | °C/W | DRB (VSON-8) package | 6 |
| Junction-to-board thermal resistance | RθJB |  | 23.3 |  | °C/W | DRB (VSON-8) package | 6 |
| Junction-to-top characterization parameter | ψJT |  | 1.1 |  | °C/W | DRB (VSON-8) package | 6 |
| Junction-to-board characterization parameter | ψJB |  | 23.5 |  | °C/W | DRB (VSON-8) package | 6 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 7 |  | °C/W | DRB (VSON-8) package | 6 |

## CAD (KiCad official)

- Symbol: `TPS7A4901DRBR`
- Footprint: `Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm`
- 3D model: SON-8-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `tps7a4901drbr-etched.step` / `tps7a4901drbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7a4901drbr.step` / `tps7a4901drbr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps7a49) (39 pp, sha256 `f69e957b22bcc2db`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps7a4901drbr-datasheet.pdf)