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TPS7A4701RGWT
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Texas Instruments Global Sourcing Parts, VQFN-20-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+58@@ -0,0 +1,58 @@+# TPS7A4701RGWT++**Texas Instruments** · Global Sourcing Parts · VQFN-20-EP(5x5)++TPS7A4701RGWT from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OUT | power_out | Regulated output voltage; minimum 10µF capacitor required between OUT and GND for stability; 47µF ceramic capacitor strongly recommended as close to device as possible. |+| 2 | NC | unconnected | No connect pin; may remain floating or be connected to any voltage between GND and IN. |+| 3 | SENSE/FB | input | Control loop error amplifier input (TPS7A4701); must connect to OUT for ANY-OUT mode operation; for adjustable mode, this is FB pin used with external feedback resistors to set output voltage. |+| 4 | 6P4V2 | input | Output offset programming pin (low-active); adds 6.4V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |+| 5 | 6P4V1 | input | Output offset programming pin (low-active); adds 6.4V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |+| 6 | 3P2V | input | Output offset programming pin (low-active); adds 3.2V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |+| 7 | GND | power_in | Ground reference and internal connection point for thermal pad; thermal pad must be soldered to large copper ground plane area for optimal thermal and mechanical performance. |+| 8 | 1P6V | input | Output offset programming pin (low-active); adds 1.6V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |+| 9 | 0P8V | input | Output offset programming pin (low-active); adds 0.8V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |+| 10 | 0P4V | input | Output offset programming pin (low-active); adds 0.4V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |+| 11 | 0P2V | input | Output offset programming pin (low-active); adds 0.2V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |+| 12 | 0P1V | input | Output offset programming pin (low-active); adds 0.1V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |+| 13 | EN | input | Enable input (CMOS logic-compatible); device enabled when voltage exceeds VEN(HI) threshold of 2.0V typical; connect to IN if independent enable control not required. |+| 14 | NR | input | Noise reduction pin; connect capacitor ≥10nF to GND for stability; 1µF ceramic capacitor recommended as close to device as possible for optimized AC performance and maximized RMS noise reduction. |+| 15 | IN | power_in | Input power supply (+3V to +36V); minimum 1µF capacitor required between IN and GND for stability; 10µF capacitor recommended as close to device as possible to reduce PCB layout sensitivity. |+| 16 | IN | power_in | Input power supply (+3V to +36V); minimum 1µF capacitor required between IN and GND for stability; 10µF capacitor recommended as close to device as possible to reduce PCB layout sensitivity. |+| 17 | NC | unconnected | No connect pin; may remain floating or be connected to any voltage between GND and IN. |+| 18 | NC | unconnected | No connect pin; may remain floating or be connected to any voltage between GND and IN. |+| 19 | NC | unconnected | No connect pin; may remain floating or be connected to any voltage between GND and IN. |+| 20 | OUT | power_out | Regulated output voltage; minimum 10µF capacitor required between OUT and GND for stability; 47µF ceramic capacitor strongly recommended as close to device as possible. |+| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-20-EP(5x5) |+| Category | Global Sourcing Parts |+| Pins | 21 |++## CAD (KiCad official)++- Symbol: `TPS7A4701RGWT`+- Footprint: `Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm`+- 3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `tps7a4701rgwt-etched.step` / `tps7a4701rgwt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7a4701rgwt.step` / `tps7a4701rgwt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps7a47) (31 pp, sha256 `8abb7994a91c0d4e`, retrieved 2026-09-26, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps7a4701rgwt-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "global sourcing parts",+ "tps7a4701rgwt",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps7a4701rgwt.kicad_sym",+ "tps7a4701rgwt.kicad_mod",+ "tps7a4701rgwt.glb",+ "tps7a4701rgwt.step",+ "tps7a4701rgwt.lbr",+ "docs/hero.png",+ "docs/tps7a4701rgwt-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "TPS7A4701RGWT",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-20-EP(5x5)",+ "pin_count": 21,+ "category": "Global Sourcing Parts",+ "subcategory": "Global Sourcing Parts",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps7a47",+ "parts": {+ "symbol": "tps7a4701rgwt.kicad_sym",+ "footprint": "tps7a4701rgwt.kicad_mod",+ "model_3d": "tps7a4701rgwt-etched.glb",+ "model_3d_plain": "tps7a4701rgwt.glb",+ "model_3d_step": "tps7a4701rgwt-etched.step",+ "model_3d_step_plain": "tps7a4701rgwt.step",+ "lbr": "tps7a4701rgwt.lbr"+ },+ "distributor_links": {+ "lcsc": "C68214",+ "digikey": "296-37243-2-ND",+ "mouser": "595-TPS7A4701RGWT"+ },+ "distributor_check": {+ "checked_at": "2026-09-26T20:50:29Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-37243-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS7A4701RGWT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "OUT",+ "type": "power_out",+ "description": "Regulated output voltage; minimum 10µF capacitor required between OUT and GND for stability; 47µF ceramic capacitor strongly recommended as close to device as possible."+ },+ {+ "number": "2",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin; may remain floating or be connected to any voltage between GND and IN."+ },+ {+ "number": "3",+ "name": "SENSE/FB",+ "type": "input",+ "description": "Control loop error amplifier input (TPS7A4701); must connect to OUT for ANY-OUT mode operation; for adjustable mode, this is FB pin used with external feedback resistors to set output voltage."+ },+ {+ "number": "4",+ "name": "6P4V2",+ "type": "input",+ "description": "Output offset programming pin (low-active); adds 6.4V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND."+ },+ {+ "number": "5",+ "name": "6P4V1",+ "type": "input",+ "description": "Output offset programming pin (low-active); adds 6.4V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND."+ },+ {+ "number": "6",+ "name": "3P2V",+ "type": "input",+ "description": "Output offset programming pin (low-active); adds 3.2V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference and internal connection point for thermal pad; thermal pad must be soldered to large copper ground plane area for optimal thermal and mechanical performance."+ },+ {+ "number": "8",+ "name": "1P6V",+ "type": "input",+ "description": "Output offset programming pin (low-active); adds 1.6V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND."+ },+ {+ "number": "9",+ "name": "0P8V",+ "type": "input",+ "description": "Output offset programming pin (low-active); adds 0.8V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND."+ },+ {+ "number": "10",+ "name": "0P4V",+ "type": "input",+ "description": "Output offset programming pin (low-active); adds 0.4V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND."+ },+ {+ "number": "11",+ "name": "0P2V",+ "type": "input",+ "description": "Output offset programming pin (low-active); adds 0.2V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND."+ },+ {+ "number": "12",+ "name": "0P1V",+ "type": "input",+ "description": "Output offset programming pin (low-active); adds 0.1V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND."+ },+ {+ "number": "13",+ "name": "EN",+ "type": "input",+ "description": "Enable input (CMOS logic-compatible); device enabled when voltage exceeds VEN(HI) threshold of 2.0V typical; connect to IN if independent enable control not required."+ },+ {+ "number": "14",+ "name": "NR",+ "type": "input",+ "description": "Noise reduction pin; connect capacitor ≥10nF to GND for stability; 1µF ceramic capacitor recommended as close to device as possible for optimized AC performance and maximized RMS noise reduction."+ },+ {+ "number": "15",+ "name": "IN",+ "type": "power_in",+ "description": "Input power supply (+3V to +36V); minimum 1µF capacitor required between IN and GND for stability; 10µF capacitor recommended as close to device as possible to reduce PCB layout sensitivity."+ },+ {+ "number": "16",+ "name": "IN",+ "type": "power_in",+ "description": "Input power supply (+3V to +36V); minimum 1µF capacitor required between IN and GND for stability; 10µF capacitor recommended as close to device as possible to reduce PCB layout sensitivity."+ },+ {+ "number": "17",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin; may remain floating or be connected to any voltage between GND and IN."+ },+ {+ "number": "18",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin; may remain floating or be connected to any voltage between GND and IN."+ },+ {+ "number": "19",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin; may remain floating or be connected to any voltage between GND and IN."+ },+ {+ "number": "20",+ "name": "OUT",+ "type": "power_out",+ "description": "Regulated output voltage; minimum 10µF capacitor required between OUT and GND for stability; 47µF ceramic capacitor strongly recommended as close to device as possible."+ },+ {+ "number": "21",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 21 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 31,+ "cost_usd": 0.3739,+ "at": "2026-09-26T20:50:13"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps7a47",+ "pages": 31,+ "sha256": "8abb7994a91c0d4e",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 21,+ "described": 21,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}