component
TPS7A4701RGWT
Public Made by Adomby adom
Texas Instruments Global Sourcing Parts, VQFN-20-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS7A4701RGWT
Texas Instruments · Global Sourcing Parts · VQFN-20-EP(5x5)
TPS7A4701RGWT from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output voltage; minimum 10µF capacitor required between OUT and GND for stability; 47µF ceramic capacitor strongly recommended as close to device as possible. |
| 2 | NC | unconnected | No connect pin; may remain floating or be connected to any voltage between GND and IN. |
| 3 | SENSE/FB | input | Control loop error amplifier input (TPS7A4701); must connect to OUT for ANY-OUT mode operation; for adjustable mode, this is FB pin used with external feedback resistors to set output voltage. |
| 4 | 6P4V2 | input | Output offset programming pin (low-active); adds 6.4V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |
| 5 | 6P4V1 | input | Output offset programming pin (low-active); adds 6.4V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |
| 6 | 3P2V | input | Output offset programming pin (low-active); adds 3.2V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |
| 7 | GND | power_in | Ground reference and internal connection point for thermal pad; thermal pad must be soldered to large copper ground plane area for optimal thermal and mechanical performance. |
| 8 | 1P6V | input | Output offset programming pin (low-active); adds 1.6V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |
| 9 | 0P8V | input | Output offset programming pin (low-active); adds 0.8V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |
| 10 | 0P4V | input | Output offset programming pin (low-active); adds 0.4V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |
| 11 | 0P2V | input | Output offset programming pin (low-active); adds 0.2V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |
| 12 | 0P1V | input | Output offset programming pin (low-active); adds 0.1V to nominal output voltage when connected to GND; leave floating if unused; do not connect voltages other than GND. |
| 13 | EN | input | Enable input (CMOS logic-compatible); device enabled when voltage exceeds VEN(HI) threshold of 2.0V typical; connect to IN if independent enable control not required. |
| 14 | NR | input | Noise reduction pin; connect capacitor ≥10nF to GND for stability; 1µF ceramic capacitor recommended as close to device as possible for optimized AC performance and maximized RMS noise reduction. |
| 15 | IN | power_in | Input power supply (+3V to +36V); minimum 1µF capacitor required between IN and GND for stability; 10µF capacitor recommended as close to device as possible to reduce PCB layout sensitivity. |
| 16 | IN | power_in | Input power supply (+3V to +36V); minimum 1µF capacitor required between IN and GND for stability; 10µF capacitor recommended as close to device as possible to reduce PCB layout sensitivity. |
| 17 | NC | unconnected | No connect pin; may remain floating or be connected to any voltage between GND and IN. |
| 18 | NC | unconnected | No connect pin; may remain floating or be connected to any voltage between GND and IN. |
| 19 | NC | unconnected | No connect pin; may remain floating or be connected to any voltage between GND and IN. |
| 20 | OUT | power_out | Regulated output voltage; minimum 10µF capacitor required between OUT and GND for stability; 47µF ceramic capacitor strongly recommended as close to device as possible. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20-EP(5x5) |
| Category | Global Sourcing Parts |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
TPS7A4701RGWT - Footprint:
Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm - 3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps7a4701rgwt-etched.step/tps7a4701rgwt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a4701rgwt.step/tps7a4701rgwt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (31 pp, sha256
8abb7994a91c0d4e, retrieved 2026-09-26, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).