component
TPS7A4701MRGWREP
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, VQFN-20-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS7A4701MRGWREP
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · VQFN-20-EP(5x5)
TPS7A4701MRGWREP from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulator output; a capacitor of 10 µF or greater must be tied from this pin to ground for stability, and a 47 µF ceramic output capacitor is highly recommended as close to the device as possible. |
| 2 | NC | unconnected | This pin can be left open or tied to any voltage between GND and IN. |
| 3 | SENSE/FB | input | Control-loop error amplifier input; in ANY-OUT mode it is the SENSE pin and must be connected to OUT at the point of load, and with external resistors it is the FB pin. |
| 4 | 6P4V2 | input | When connected to GND it adds 6.4 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 5 | 6P4V1 | input | When connected to GND it adds 6.4 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 6 | 3P2V | input | When connected to GND it adds 3.2 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 7 | GND | power_in | Ground; the thermal pad is internally connected to GND and should be tied to a large-area ground plane. |
| 8 | 1P6V | input | When connected to GND it adds 1.6 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 9 | 0P8V | input | When connected to GND it adds 0.8 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 10 | 0P4V | input | When connected to GND it adds 0.4 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 11 | 0P2V | input | When connected to GND it adds 0.2 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 12 | 0P1V | input | When connected to GND it adds 0.1 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 13 | EN | input | Enable pin; the device is enabled when the voltage exceeds the maximum enable voltage VEN(HI), and EN must be tied to IN if enable is not required. |
| 14 | NR | passive | Noise reduction pin; a capacitor of 10 nF or greater must be tied from this pin to ground for stability, and 1 µF is recommended to maximize AC performance and minimize noise. |
| 15 | IN | power_in | Input supply; a capacitor of 1 µF or greater must be tied from this pin to ground for stability, with 10 µF recommended as close to the device as possible. |
| 16 | IN | power_in | Input supply; a capacitor of 1 µF or greater must be tied from this pin to ground for stability, with 10 µF recommended as close to the device as possible. |
| 17 | NC | unconnected | This pin can be left open or tied to any voltage between GND and IN. |
| 18 | NC | unconnected | This pin can be left open or tied to any voltage between GND and IN. |
| 19 | NC | unconnected | This pin can be left open or tied to any voltage between GND and IN. |
| 20 | OUT | power_out | Regulator output; a capacitor of 10 µF or greater must be tied from this pin to ground for stability, and a 47 µF ceramic output capacitor is highly recommended as close to the device as possible. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| IN pin to GND pin voltage | -0.4 | 36 | V | 4 | |||
| EN pin to GND pin voltage | -0.4 | 36 | V | 4 | |||
| EN pin to IN pin voltage | -36 | 0.4 | V | 4 | |||
| OUT pin to GND pin voltage | -0.4 | 36 | V | 4 | |||
| NR pin to GND pin voltage | -0.4 | 36 | V | 4 | |||
| SENSE/FB pin to GND pin voltage | -0.4 | 36 | V | 4 | |||
| 0P1V pin to GND pin voltage | -0.4 | 36 | V | 4 | |||
| 0P2V pin to GND pin voltage | -0.4 | 36 | V | 4 | |||
| 0P4V pin to GND pin voltage | -0.4 | 36 | V | 4 | |||
| 0P8V pin to GND pin voltage | -0.4 | 36 | V | 4 | |||
| 1P6V pin to GND pin voltage | -0.4 | 36 | V | 4 | |||
| 3P2V pin to GND pin voltage | -0.4 | 36 | V | 4 | |||
| 6P4V1 pin to GND pin voltage | -0.4 | 36 | V | 4 | |||
| 6P4V2 pin to GND pin voltage | -0.4 | 36 | V | 4 | |||
| Operating virtual junction temperature | TJ | -55 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Input voltage (VI) | VI | 3 | 35 | V | 5 | ||
| Output voltage (VO) | VO | 1.4 | 34 | V | 5 | ||
| Enable voltage (VEN) | VEN | 0 | V | Maximum printed as VIN | 5 | ||
| Output current (IO) | IO | 0 | 1 | A | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 32.5 | °C/W | RGW 20-pin VQFN | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 27 | °C/W | RGW 20-pin VQFN | 5 | ||
| Junction-to-board thermal resistance | RθJB | 11.9 | °C/W | RGW 20-pin VQFN | 5 | ||
| Junction-to-top characterization parameter | ψJT | 0.3 | °C/W | RGW 20-pin VQFN | 5 | ||
| Junction-to-board characterization parameter | ψJB | 11.9 | °C/W | RGW 20-pin VQFN | 5 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 1.7 | °C/W | RGW 20-pin VQFN | 5 | ||
| Input voltage range | VI | 3 | 35 | V | 6 | ||
| Output voltage range (ANY-OUT option) | VO | 1.4 | 20.5 | V | VI ≥ VO(nom) + 1 V or 3 V (whichever is greater), COUT = 20 µF | 6 | |
| Output voltage range (adjustable option) | VO | 1.4 | 34 | V | VI ≥ VO(nom) + 1 V or 3 V (whichever is greater), COUT = 20 µF | 6 | |
| Nominal accuracy | -1 | 1 | %VO | TJ = 25°C, COUT = 20 µF | 6 | ||
| Overall accuracy | -3.5 | 3.5 | %VO | VO(nom) + 1 V ≤ VI ≤ 35 V, 0 mA ≤ IO ≤ 1 A, COUT = 20 µF | 6 | ||
| Dropout voltage | V(DO) | 307 | 450 | mV | VI = 95% VO(nom), IO = 1 A | 6 | |
| Current limit | I(CL) | 1 | 1.26 | A | VO = 90% VO(nom) | 6 | |
| Ground pin current | I(GND) | 0.58 | 1 | mA | IO = 0 mA | 6 | |
| Enable pin current | I(EN) | 0.78 | 2 | µA | VEN = VI | 6 | |
| Enable pin current | I(EN) | 0.81 | 2 | µA | VI = VEN = 35 V | 6 | |
| Shutdown supply current | I(SHDN) | 2.55 | 8 | µA | VEN = 0.4 V | 6 | |
| Shutdown supply current | I(SHDN) | 3.04 | 60 | µA | VEN = 0.4 V, VI = 35 V | 6 | |
| Enable high-level voltage | V+EN(HI) | 2 | V | 6 | |||
| Enable low-level voltage | V+EN(LO) | 0 | 0.4 | V | 6 | ||
| Feedback pin current | I(FB) | 350 | nA | 6 | |||
| Operating junction temperature | TJ | -55 | 125 | °C | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | input and output capacitor, and to the LDO ground pin, must also be as close to each other as possible and connected by a wide, component-side, copper surface. The use of vias and long traces to creat | 20 |
CAD (KiCad official)
- Symbol:
TPS7A4701MRGWREP - Footprint:
Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm - 3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps7a4701mrgwrep-etched.step/tps7a4701mrgwrep-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a4701mrgwrep.step/tps7a4701mrgwrep.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
95957733a7391aca, retrieved 2026-10-20, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS7A4701MRGWREP
**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · VQFN-20-EP(5x5)
TPS7A4701MRGWREP from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulator output; a capacitor of 10 µF or greater must be tied from this pin to ground for stability, and a 47 µF ceramic output capacitor is highly recommended as close to the device as possible. |
| 2 | NC | unconnected | This pin can be left open or tied to any voltage between GND and IN. |
| 3 | SENSE/FB | input | Control-loop error amplifier input; in ANY-OUT mode it is the SENSE pin and must be connected to OUT at the point of load, and with external resistors it is the FB pin. |
| 4 | 6P4V2 | input | When connected to GND it adds 6.4 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 5 | 6P4V1 | input | When connected to GND it adds 6.4 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 6 | 3P2V | input | When connected to GND it adds 3.2 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 7 | GND | power_in | Ground; the thermal pad is internally connected to GND and should be tied to a large-area ground plane. |
| 8 | 1P6V | input | When connected to GND it adds 1.6 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 9 | 0P8V | input | When connected to GND it adds 0.8 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 10 | 0P4V | input | When connected to GND it adds 0.4 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 11 | 0P2V | input | When connected to GND it adds 0.2 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 12 | 0P1V | input | When connected to GND it adds 0.1 V to the nominal output voltage; do not connect any voltage other than GND, and leave floating if unused. |
| 13 | EN | input | Enable pin; the device is enabled when the voltage exceeds the maximum enable voltage VEN(HI), and EN must be tied to IN if enable is not required. |
| 14 | NR | passive | Noise reduction pin; a capacitor of 10 nF or greater must be tied from this pin to ground for stability, and 1 µF is recommended to maximize AC performance and minimize noise. |
| 15 | IN | power_in | Input supply; a capacitor of 1 µF or greater must be tied from this pin to ground for stability, with 10 µF recommended as close to the device as possible. |
| 16 | IN | power_in | Input supply; a capacitor of 1 µF or greater must be tied from this pin to ground for stability, with 10 µF recommended as close to the device as possible. |
| 17 | NC | unconnected | This pin can be left open or tied to any voltage between GND and IN. |
| 18 | NC | unconnected | This pin can be left open or tied to any voltage between GND and IN. |
| 19 | NC | unconnected | This pin can be left open or tied to any voltage between GND and IN. |
| 20 | OUT | power_out | Regulator output; a capacitor of 10 µF or greater must be tied from this pin to ground for stability, and a 47 µF ceramic output capacitor is highly recommended as close to the device as possible. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| IN pin to GND pin voltage | | -0.4 | | 36 | V | | 4 |
| EN pin to GND pin voltage | | -0.4 | | 36 | V | | 4 |
| EN pin to IN pin voltage | | -36 | | 0.4 | V | | 4 |
| OUT pin to GND pin voltage | | -0.4 | | 36 | V | | 4 |
| NR pin to GND pin voltage | | -0.4 | | 36 | V | | 4 |
| SENSE/FB pin to GND pin voltage | | -0.4 | | 36 | V | | 4 |
| 0P1V pin to GND pin voltage | | -0.4 | | 36 | V | | 4 |
| 0P2V pin to GND pin voltage | | -0.4 | | 36 | V | | 4 |
| 0P4V pin to GND pin voltage | | -0.4 | | 36 | V | | 4 |
| 0P8V pin to GND pin voltage | | -0.4 | | 36 | V | | 4 |
| 1P6V pin to GND pin voltage | | -0.4 | | 36 | V | | 4 |
| 3P2V pin to GND pin voltage | | -0.4 | | 36 | V | | 4 |
| 6P4V1 pin to GND pin voltage | | -0.4 | | 36 | V | | 4 |
| 6P4V2 pin to GND pin voltage | | -0.4 | | 36 | V | | 4 |
| Operating virtual junction temperature | TJ | -55 | | 150 | °C | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Input voltage (VI) | VI | 3 | | 35 | V | | 5 |
| Output voltage (VO) | VO | 1.4 | | 34 | V | | 5 |
| Enable voltage (VEN) | VEN | 0 | | | V | Maximum printed as VIN | 5 |
| Output current (IO) | IO | 0 | | 1 | A | | 5 |
| Junction-to-ambient thermal resistance | RθJA | | 32.5 | | °C/W | RGW 20-pin VQFN | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 27 | | °C/W | RGW 20-pin VQFN | 5 |
| Junction-to-board thermal resistance | RθJB | | 11.9 | | °C/W | RGW 20-pin VQFN | 5 |
| Junction-to-top characterization parameter | ψJT | | 0.3 | | °C/W | RGW 20-pin VQFN | 5 |
| Junction-to-board characterization parameter | ψJB | | 11.9 | | °C/W | RGW 20-pin VQFN | 5 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | | 1.7 | | °C/W | RGW 20-pin VQFN | 5 |
| Input voltage range | VI | 3 | | 35 | V | | 6 |
| Output voltage range (ANY-OUT option) | VO | 1.4 | | 20.5 | V | VI ≥ VO(nom) + 1 V or 3 V (whichever is greater), COUT = 20 µF | 6 |
| Output voltage range (adjustable option) | VO | 1.4 | | 34 | V | VI ≥ VO(nom) + 1 V or 3 V (whichever is greater), COUT = 20 µF | 6 |
| Nominal accuracy | | -1 | | 1 | %VO | TJ = 25°C, COUT = 20 µF | 6 |
| Overall accuracy | | -3.5 | | 3.5 | %VO | VO(nom) + 1 V ≤ VI ≤ 35 V, 0 mA ≤ IO ≤ 1 A, COUT = 20 µF | 6 |
| Dropout voltage | V(DO) | | 307 | 450 | mV | VI = 95% VO(nom), IO = 1 A | 6 |
| Current limit | I(CL) | 1 | | 1.26 | A | VO = 90% VO(nom) | 6 |
| Ground pin current | I(GND) | | 0.58 | 1 | mA | IO = 0 mA | 6 |
| Enable pin current | I(EN) | | 0.78 | 2 | µA | VEN = VI | 6 |
| Enable pin current | I(EN) | | 0.81 | 2 | µA | VI = VEN = 35 V | 6 |
| Shutdown supply current | I(SHDN) | | 2.55 | 8 | µA | VEN = 0.4 V | 6 |
| Shutdown supply current | I(SHDN) | | 3.04 | 60 | µA | VEN = 0.4 V, VI = 35 V | 6 |
| Enable high-level voltage | V+EN(HI) | 2 | | | V | | 6 |
| Enable low-level voltage | V+EN(LO) | 0 | | 0.4 | V | | 6 |
| Feedback pin current | I(FB) | | 350 | | nA | | 6 |
| Operating junction temperature | TJ | -55 | | 125 | °C | | 6 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | input and output capacitor, and to the LDO ground pin, must also be as close to each other as possible and connected by a wide, component-side, copper surface. The use of vias and long traces to creat | 20 |
## CAD (KiCad official)
- Symbol: `TPS7A4701MRGWREP`
- Footprint: `Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm`
- 3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `tps7a4701mrgwrep-etched.step` / `tps7a4701mrgwrep-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7a4701mrgwrep.step` / `tps7a4701mrgwrep.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps7a4701-ep) (29 pp, sha256 `95957733a7391aca`, retrieved 2026-10-20, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps7a4701mrgwrep-datasheet.pdf)