TPS7A4401DGQR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HVSSOP-10

TPS7A4401DGQR from Texas Instruments, in a HVSSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUT	output	Main regulated output that needs a capacitor from OUT to ground for stability, with a recommended COUT of 1 µF to 100 µF (2.2 µF nominal, derated to 50%), and VOUT for the adjustable version is 1.24 V up to VMID_OUT − VDO(OUT).
2	FB	input	Feedback input to the control-loop error amplifier that sets the OUT voltage through external resistors, is used only on the adjustable version, and must not be left floating.
3	PG	output	Open-drain power-good output that indicates when the output reaches VIT(PG, RISING); it has a maximum of 18 V recommended, requires a pullup resistor to limit sink current when driven low, and can be left floating or tied to GND if unused.
4	MVSEL1	input	MID_OUT voltage-select input that is used together with MVSEL2 to set VMID_OUT (10 V, 12 V or 15 V); it must not be floated and should be tied to GND if not used, with a recommended range of 0 V to 18 V.
5	GND	power_in	Ground pin; all voltages in the absolute maximum ratings are referenced to GND.
6	EN	input	Precision enable input where driving above VEN(HI) enables the device and driving below VEN(LOW) disables it, with a recommended range of 0 V to 18 V; it can be left floating because of an internal pullup, and if tied to IN, VIN must not exceed 18 V.
7	MVSEL2	input	MID_OUT voltage-select input that is used together with MVSEL1 to set VMID_OUT (10 V, 12 V or 15 V); it must not be floated and should be tied to GND if not used, with a recommended range of 0 V to 18 V.
8	MID_OUT	output	Second (MID) regulated output that needs a capacitor to ground for stability, with CMID_OUT of 3 × COUT (maintain a 3:1 ratio), and it shares the 50 mA maximum output current with OUT.
9	NC	unconnected	No internal connection; this pin must be left floating to observe high-voltage clearance between the IN and MID_OUT pins.
10	IN	input	Input pin with a recommended ceramic capacitor (0.1 µF minimum) from IN to ground placed close to the pins; VIN is 4 V to 65 V, with 85 V absolute maximum for 200 ms.
11	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HVSSOP-10
Category	Power Management (PMIC)
Pins	11

CAD (KiCad official)

Symbol: TPS7A4401DGQR
Footprint: Package_SO:HVSSOP-10-1EP_3x3mm_P0.5mm_EP1.83x1.89mm
3D model: HVSSOP-10, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.0 mm nominal HVSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: tps7a4401dgqr-etched.step / tps7a4401dgqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7a4401dgqr.step / tps7a4401dgqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (35 pp, sha256 83dc5cd7eb0a0b86, retrieved 2026-10-11, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# TPS7A4401DGQR

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HVSSOP-10

TPS7A4401DGQR from Texas Instruments, in a HVSSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Main regulated output that needs a capacitor from OUT to ground for stability, with a recommended COUT of 1 µF to 100 µF (2.2 µF nominal, derated to 50%), and VOUT for the adjustable version is 1.24 V up to VMID_OUT − VDO(OUT). |
| 2 | FB | input | Feedback input to the control-loop error amplifier that sets the OUT voltage through external resistors, is used only on the adjustable version, and must not be left floating. |
| 3 | PG | output | Open-drain power-good output that indicates when the output reaches VIT(PG, RISING); it has a maximum of 18 V recommended, requires a pullup resistor to limit sink current when driven low, and can be left floating or tied to GND if unused. |
| 4 | MVSEL1 | input | MID_OUT voltage-select input that is used together with MVSEL2 to set VMID_OUT (10 V, 12 V or 15 V); it must not be floated and should be tied to GND if not used, with a recommended range of 0 V to 18 V. |
| 5 | GND | power_in | Ground pin; all voltages in the absolute maximum ratings are referenced to GND. |
| 6 | EN | input | Precision enable input where driving above VEN(HI) enables the device and driving below VEN(LOW) disables it, with a recommended range of 0 V to 18 V; it can be left floating because of an internal pullup, and if tied to IN, VIN must not exceed 18 V. |
| 7 | MVSEL2 | input | MID_OUT voltage-select input that is used together with MVSEL1 to set VMID_OUT (10 V, 12 V or 15 V); it must not be floated and should be tied to GND if not used, with a recommended range of 0 V to 18 V. |
| 8 | MID_OUT | output | Second (MID) regulated output that needs a capacitor to ground for stability, with CMID_OUT of 3 × COUT (maintain a 3:1 ratio), and it shares the 50 mA maximum output current with OUT. |
| 9 | NC | unconnected | No internal connection; this pin must be left floating to observe high-voltage clearance between the IN and MID_OUT pins. |
| 10 | IN | input | Input pin with a recommended ceramic capacitor (0.1 µF minimum) from IN to ground placed close to the pins; VIN is 4 V to 65 V, with 85 V absolute maximum for 200 ms. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVSSOP-10 |
| Category | Power Management (PMIC) |
| Pins | 11 |

## CAD (KiCad official)

- Symbol: `TPS7A4401DGQR`
- Footprint: `Package_SO:HVSSOP-10-1EP_3x3mm_P0.5mm_EP1.83x1.89mm`
- 3D model: HVSSOP-10, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.0 mm nominal HVSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tps7a4401dgqr-etched.step` / `tps7a4401dgqr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7a4401dgqr.step` / `tps7a4401dgqr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps7a44) (35 pp, sha256 `83dc5cd7eb0a0b86`, retrieved 2026-10-11, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps7a4401dgqr-datasheet.pdf)