component
TPS7A4001DGNT
Public Made by Adomby adom
JSMSEMI Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, HVSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS7A4001DGNT
JSMSEMI · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HVSSOP-8
TPS7A4001DGNT from JSMSEMI, in a HVSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output voltage pin, adjustable from 1.2V to 90V, stable with output capacitance greater than 2.2µF. |
| 2 | FB | input | Feedback pin with 0.8V internal reference (VREF) used to set the output voltage via a resistor divider; absolute maximum -0.3V to 5.5V. |
| 3 | NC | unconnected | No connect pin, not internally connected. |
| 4 | GND | power_in | Ground pin. |
| 5 | EN | input | Enable pin compatible with standard CMOS logic, high level above 1.0V enables the regulator and low level below 0.4V gives low-current shutdown, 0V to 100V recommended. |
| 6 | NC | unconnected | No connect pin, not internally connected. |
| 7 | NC | unconnected | No connect pin, not internally connected. |
| 8 | IN | power_in | Input voltage pin, operating range 7V to 100V with absolute maximum of 110V, requires input capacitance greater than 0.47µF. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | JSMSEMI |
| Package | HVSSOP-8 |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Shutdown temperature (temperature increasing) | 160 | ℃ | Shutdown, temperature increasing | 3 | |||
| Reset temperature (temperature decreasing) | 140 | ℃ | Reset, temperature decreasing | 3 | |||
| Input Voltage | VIN | 7 | 100 | V | 3 | ||
| Output Voltage | VOUT | 1.2 | 90 | V | 3 | ||
| Enable Voltage | VEN | 0 | 100 | V | 3 | ||
| Output Current | IOUT | 0 | 50 | mA | 3 | ||
| Junction Temperature (operating) | -40 | 125 | °C | 3 | |||
| Input Voltage (absolute maximum) | VIN | -0.3 | 110 | V | 3 | ||
| Output Voltage (absolute maximum) | VOUT | -0.3 | 110 | V | 3 | ||
| FB pin voltage (absolute maximum) | -0.3 | 5.5 | V | 3 | |||
| EN pin voltage (absolute maximum) | EN | -0.3 | 110 | V | 3 | ||
| Junction Temperature (absolute maximum) | 125 | °C | 3 | ||||
| Lead Temperature (soldering, 10 sec) | 300 | °C | 3 | ||||
| Storage Temperature | -65 | 150 | °C | 3 | |||
| Input Voltage | VIN | 7 | 100 | V | 3 | ||
| Internal Reference Voltage | VREF | 0.788 | 0.8 | 0.812 | V | 3 | |
| Line Regulation | ΔVLINE | 3 | 20 | mV | VIN=7V to 100V, 100uA < IOUT < 50mA | 3 | |
| Load Regulation | ΔVLOAD | 20 | mV | IOUT=20mA | 3 | ||
| Load Regulation | ΔVLOAD | 50 | mV | IOUT=50mA | 3 | ||
| Dropout Voltage | VDROP | 1000 | mV | IOUT=20mA | 3 | ||
| Dropout Voltage | VDROP | 2800 | mV | IOUT=50mA | 3 | ||
| Quiescent Current | IQ | 23 | 40 | uA | IOUT = 0mA | 3 | |
| Shutdown Current | ISD | 8 | 15 | uA | VEN = 0V | 3 | |
| Current Limit | ICL | 55 | 120 | 200 | mA | VOUT = 90% VOUT(NOM) | 3 |
| Enable High Level | VENHI | 1 | V | 3 | |||
| Enable Low Level | VENLO | 0 | 0.4 | V | 3 | ||
| Enable Pin Current | IEN | 0.02 | 1 | uA | 7V<VIN<100V, VIN=VEN | 3 | |
| Feedback Pin Current | IFB | 0.01 | 0.11 | uA | 3 |
CAD (KiCad official)
- Symbol:
TPS7A4001DGNT - Footprint:
Package_SO:HVSSOP-8-1EP_3x3mm_P0.65mm_EP1.57x1.89mm - 3D model: HVSSOP-8, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.0 mm nominal HVSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps7a4001dgnt-etched.step/tps7a4001dgnt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a4001dgnt.step/tps7a4001dgnt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: JSMSEMI datasheet (5 pp, sha256
7bfe0c20360731da, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).