component

TPS7A2430DBVR

Public Made by Adom

by adom

Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps7a2430dbvrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs tps7a2430dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers tps7a2430dbvr: viewers · Ray 1mo ago
package.json tps7a2430dbvr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json tps7a2430dbvr: specified limits as data (metadata.characteristics, 28 rows from the datasheet) · Ray 26d ago
README.md tps7a2430dbvr: specified limits as data (metadata.characteristics, 28 rows from the datasheet) · Ray 26d ago
tps7a2430dbvr-etched.fit.json tps7a2430dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps7a2430dbvr-etched.glb tps7a2430dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps7a2430dbvr-etched.step tps7a2430dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps7a2430dbvr.glb Publish 0.1.0 · Ray 1mo ago
tps7a2430dbvr.kicad_mod Publish 0.1.0 · Ray 1mo ago
tps7a2430dbvr.kicad_sym Publish 0.1.0 · Ray 1mo ago
tps7a2430dbvr.lbr Publish 0.1.0 · Ray 1mo ago
tps7a2430dbvr.step Publish 0.1.0 · Ray 1mo ago

TPS7A2430DBVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS7A2430DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Supply input pin accepting 2.4V to 18V with typical quiescent current of 2.0µA; place 1µF or larger capacitor close to IN and GND for best transient response and input impedance minimization.
2 GND power_in Ground reference pin (negative supply).
3 EN input Active-high enable pin; drive EN greater than 0.9V to enable regulator or less than 0.4V to shutdown; do not float this pin or connect to IN if unused.
4 NC unconnected No internal connection in fixed-voltage version; can float or tie to GND for improved thermal performance.
5 OUT power_out Regulated 3.0V output pin with ±1.25% accuracy and 200mA maximum output current; requires 1µF to 100µF output capacitor close to OUT and GND for stability.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage accuracy, fixed output versions (TJ = -40 to 125°C) VOUT -1.25 1.25 % Fixed output versions, TJ = -40℃ to 125℃ 6
Output voltage accuracy, fixed output versions (TJ = 25°C) VOUT -0.5 0.5 % Fixed output versions, TJ = 25℃ 6
Line regulation ΔVOUT(ΔVIN) -0.25 0.25 % (VOUT(nom) + 0.5 V or 2.4 V) ≤ VIN ≤ 18 V 6
Load regulation ΔVOUT(ΔIOUT) -0.5 0.5 % 1 mA ≤ IOUT ≤ 200 mA 6
Ground pin current IGND 2 4.5 µA IOUT = 0 mA 6
Shutdown current ISHUTDOWN 325 650 nA VEN ≤ 0.4 V, VIN = 2.4 V, Iout = 0 mA 6
Output current limit ICL 250 410 620 mA VOUT = 0.9 × VOUT(nom) 6
Dropout voltage VDO 110 160 mV IOUT = 100 mA 6
Dropout voltage VDO 160 250 mV IOUT = 200 mA 6
UVLO threshold rising VUVLO(RISING) 1.95 2.15 2.35 V VIN rising 6
UVLO threshold falling VUVLO(FALLING) 1.85 2.09 2.25 V VIN falling 6
Input voltage (absolute maximum) VIN -0.3 20 V 4
Output voltage (absolute maximum) VOUT -0.3 V 4
Enable voltage (absolute maximum) VEN -0.3 20 V 4
Operating junction temperature (absolute maximum) TJ -50 150 °C 4
Storage temperature (absolute maximum) Tstg -65 150 °C 4
Input voltage (recommended) VIN 2.4 18 V 5
Output voltage, fixed version (recommended) VOUT 1.25 5.5 V Fixed version 5
Output current (recommended) IOUT 0 200 mA 5
Enable voltage (recommended) VEN 0 18 V 5
Output capacitor (recommended) COUT 1 2.2 100 µF Assumed to derate to 50% of nominal value 5
Operating junction temperature (recommended) TJ -40 125 °C 5
Input capacitor (recommended nominal) CIN 1 µF Assumed to derate to 50% of nominal value 5
Junction-to-ambient thermal resistance RθJA 167.8 °C/W DBV (SOT23-5) package 5
Junction-to-case (top) thermal resistance RθJC(top) 86.7 °C/W DBV (SOT23-5) package 5
Junction-to-board thermal resistance RθJB 38.4 °C/W DBV (SOT23-5) package 5
Junction-to-top characterization parameter ψJT 14.5 °C/W DBV (SOT23-5) package 5
Junction-to-board characterization parameter ψJB 38.1 °C/W DBV (SOT23-5) package 5

CAD (KiCad official)

  • Symbol: TPS7A2430DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps7a2430dbvr-etched.step / tps7a2430dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7a2430dbvr.step / tps7a2430dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 8c6a0352ce73fc7b, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF