# TPS7A2401DBVR

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS7A2401DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input pin; supply voltage range 2.4 V to 18 V; minimum 1 µF input capacitor required from IN to ground for best transient response. |
| 2 | GND | power_in | Ground reference pin. |
| 3 | EN | input | Enable pin (active-high); device enabled when EN > 0.9 V, disabled when EN < 0.4 V; do not leave floating; connect to IN if enable control not needed. |
| 4 | FB | input | Feedback input pin to control-loop error amplifier for adjustable-voltage version; maximum FB pin current 10 nA; external resistors R1 and R2 set output voltage per VOUT = VFB × (1 + R1/R2). |
| 5 | OUT | power_out | Output pin; requires 1 to 2.2 µF output capacitor for stability (up to 100 µF maximum); regulated output voltage 1.24 V to 17.75 V (adjustable version) at maximum 200 mA output current. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage accuracy (adjustable version) | VOUT | 1.22 | 1.24 | 1.26 | V | Adjustable version, VOUT = VFB | 6 |
| Line regulation | ΔVOUT(ΔVIN) | -0.25 |  | 0.25 | % | (VOUT(nom) + 0.5 V or 2.4 V) ≤ VIN ≤ 18 V | 6 |
| Load regulation | ΔVOUT(ΔIOUT) | -0.5 |  | 0.5 | % | 1 mA ≤ IOUT ≤ 200 mA | 6 |
| Ground pin current | IGND |  | 2 | 4.5 | µA | IOUT = 0 mA | 6 |
| Shutdown current | ISHUTDOWN |  | 325 | 650 | nA | VEN ≤ 0.4 V, VIN = 2.4 V, Iout = 0 mA | 6 |
| Output current limit | ICL | 250 | 410 | 620 | mA | VOUT = 0.9 × VOUT(nom) | 6 |
| Dropout voltage | VDO |  | 110 | 160 | mV | IOUT = 100 mA | 6 |
| Dropout voltage | VDO |  | 160 | 250 | mV | IOUT = 200 mA | 6 |
| UVLO threshold rising | VUVLO(RISING) | 1.95 | 2.15 | 2.35 | V | VIN rising | 6 |
| UVLO threshold falling | VUVLO(FALLING) | 1.85 | 2.09 | 2.25 | V | VIN falling | 6 |
| Enable pin low-level input voltage | VEN(LOW) |  |  | 0.4 | V | Device disabled | 6 |
| Input voltage | VIN | -0.3 |  | 20 | V | All voltages with respect to GND | 4 |
| Output voltage | VOUT | -0.3 |  |  | V | Max = VIN + 0.3 V or 20 V (whichever is smaller); all voltages with respect to GND | 4 |
| Feedback voltage | VFB | -0.3 |  | 5.5 | V | All voltages with respect to GND | 4 |
| Enable voltage | VEN | -0.3 |  | 20 | V | All voltages with respect to GND | 4 |
| Operating junction temperature | TJ | -50 |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Input voltage | VIN | 2.4 |  | 18 | V |  | 5 |
| Output voltage (adjustable version) | VOUT | 1.24 |  |  | V | Adjustable version; max = 18 - VDO | 5 |
| Output current | IOUT | 0 |  | 200 | mA |  | 5 |
| Enable voltage | VEN | 0 |  | 18 | V |  | 5 |
| Output capacitor | COUT | 1 | 2.2 | 100 | μF | All capacitor values assumed to derate to 50% of nominal | 5 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 5 |
| Ground pin current | IGND |  | 15 |  | µA | IOUT = 1 mA | 6 |
| UVLO hysteresis | VUVLO(HYS) |  | 70 |  | mV |  | 6 |
| Output voltage noise | Vn |  | 300 |  | μVRMS | BW = 10 Hz to 100 kHz, VOUT = 1.24 V | 6 |
| Enable pin high-level input voltage | VEN(HI) |  | 0.9 |  | V | Device enabled | 6 |
| EN pin current | IEN |  | 10 |  | nA | VEN = 18 V | 6 |
| Thermal shutdown temperature | TSD(shutdown) |  | 165 |  | °C | Shutdown, temperature increasing | 6 |
| Thermal shutdown reset temperature | TSD(reset) |  | 145 |  | °C | Reset, temperature decreasing | 6 |
| Feedback voltage | VFB |  | 1.24 |  | V | Adjustable version only | 6 |
| FB pin current | IFB |  | 10 |  | nA |  | 6 |
| Power-supply rejection ratio | PSRR |  | 75 |  | dB | f = 10 Hz | 6 |
| Power-supply rejection ratio | PSRR |  | 70 |  | dB | f = 100 Hz | 6 |
| Power-supply rejection ratio | PSRR |  | 62 |  | dB | f = 1 kHz | 6 |
| Input capacitor | CIN |  | 1 |  | μF | All capacitor values assumed to derate to 50% of nominal | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 167.8 |  | °C/W |  | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 86.7 |  | °C/W |  | 5 |
| Junction-to-board thermal resistance | RθJB |  | 38.4 |  | °C/W |  | 5 |
| Junction-to-top characterization parameter | ψJT |  | 14.5 |  | °C/W |  | 5 |
| Junction-to-board characterization parameter | ψJB |  | 38.1 |  | °C/W |  | 5 |

## CAD (KiCad official)

- Symbol: `TPS7A2401DBVR`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `tps7a2401dbvr-etched.step` / `tps7a2401dbvr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7a2401dbvr.step` / `tps7a2401dbvr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps7a24) (31 pp, sha256 `8c6a0352ce73fc7b`, retrieved 2026-09-23, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps7a2401dbvr-datasheet.pdf)