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TPS7A2045PDBVR

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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TPS7A2045PDBVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS7A2045PDBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input voltage supply, 1.6 V to 6.0 V. Place input capacitor (typ 1 μF) as close to IN and GND as possible to minimize input impedance.
2 GND power_in Common ground reference for the device.
3 EN input Enable input. VEN > VEN(HI) (0.9 V typ) turns the regulator on; VEN < VEN(LOW) (0.3 V max) disables the regulator and discharges VOUT to GND. Internal 500 kΩ pulldown holds the regulator off by default; the pulldown is disconnected when EN is high to reduce input current.
4 NC unconnected No internal electrical connection.
5 OUT power_out Regulated output voltage (4.5 V nominal for TPS7A2045). Requires a low-ESR output capacitor (typ 1 μF, 0.47 μF min to 200 μF max, ESR ≤ 100 mΩ) to GND for stability. Internal 150 Ω (typ) pulldown discharges VOUT when the regulator is in shutdown.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category PMIC
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • TPS7A2045PDBVR
  • TPS7A2045PDBVRDBVT
  • TPS7A2045PDBVRDQNR
  • TPS7A2045PDBVRYCJR
  • TPS7A2045PDBVRYCKR

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input supply voltage VIN 1.6 6 V 5
Enable input voltage VEN 0 6 V 5
Nominal output voltage range (family range, all 0.8 V to 5.5 V variants) VOUT 0.8 5.5 V 5
Output current IOUT 0 300 mA 5
Operating junction temperature TJ -40 125 °C 5
Input supply voltage (absolute max) VIN -0.3 6.5 V 5
Output voltage (absolute max) VOUT -0.3 6.5 V Printed max is 6.5 or VIN + 0.3 (lesser of the two applies) 5
Enable input voltage (absolute max) VEN -0.3 6.5 V 5
Operating junction temperature (absolute max) TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
Junction-to-ambient thermal resistance (DBV SOT-23) RθJA 187.1 °C/W 6
Junction-to-case (top) thermal resistance (DBV SOT-23) RθJC(top) 85.5 °C/W 6
Junction-to-board thermal resistance (DBV SOT-23) RθJB 54.4 °C/W 6
Junction-to-top characterization parameter (DBV SOT-23) ψJT 27.1 °C/W 6
Junction-to-board characterization parameter (DBV SOT-23) ψJB 54.1 °C/W 6
Output voltage tolerance (DBV, VOUT ≥ 2.8 V) ΔVOUT -1.5 1.5 % VIN = (VOUT(NOM) + 0.3 V) to 6.0 V, IOUT = 1 mA to 300 mA, VOUT ≥ 2.8 V (DBV package) 6
Quiescent ground current IGND 6.5 8.5 µA VEN = VIN = 6 V, IOUT = 0 mA, TJ = 25°C 6
Quiescent ground current IGND 10 µA VEN = VIN = 6 V, IOUT = 0 mA, TJ = –40°C to 85°C 6
Quiescent ground current IGND 15 µA VEN = VIN = 6 V, IOUT = 0 mA, TJ = –40°C to 125°C 6
Shutdown ground current ISHDN 0.07 0.2 µA VEN = 0 V (disabled), VIN = 6.0 V, TJ = 25°C 6
Ground current in dropout IGND(DO) 6.5 15 µA VIN ≤ VOUT(NOM), IOUT = 0 mA, VEN = VIN 6
Dropout voltage (2.5 V ≤ VOUT < 5.5 V, DBV) VDO 145 mV IOUT = 300 mA, VOUT = 95% x VOUT(NOM), 2.5 V ≤ VOUT < 5.5 V (DBV) 6
UVLO threshold, VIN rising (DBV and DQN) VUVLO 1.17 1.35 1.59 V VIN rising (DBV and DQN packages) 7
UVLO threshold, VIN falling (DBV and DQN) VUVLO 1.11 1.3 1.55 V VIN falling (DBV and DQN packages) 7
Thermal shutdown, TJ rising (typical per text) TSD 165 °C TJ rising 7
Thermal shutdown reset, TJ falling (typical per text) TSD 140 °C TJ falling 7

CAD (KiCad official)

  • Symbol: TPS7A2045PDBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps7a2045pdbvr-etched.step / tps7a2045pdbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7a2045pdbvr.step / tps7a2045pdbvr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tps7a2045pdbvr.step 85 KB You want the bare part, or you mark your own boards.
tps7a2045pdbvr-etched.step 2.4 MB You want the part with TPS7A2045PDBVR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 592 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (57 pp, sha256 0c6942715f398ba4, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF