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docs tps7a2009pdbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers tps7a2009pdbvr: viewers · Ray 1mo ago
package.json tps7a2009pdbvr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json tps7a2009pdbvr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md Initial commit: component/tps7a2009pdbvr · Ray 1mo ago
tps7a2009pdbvr-etched.fit.json tps7a2009pdbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps7a2009pdbvr-etched.glb tps7a2009pdbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps7a2009pdbvr-etched.step tps7a2009pdbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps7a2009pdbvr.glb Publish 0.1.0 · Ray 1mo ago
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tps7a2009pdbvr.kicad_sym Publish 0.1.0 · Ray 1mo ago
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tps7a2009pdbvr.step Publish 0.1.0 · Ray 1mo ago

TPS7A2009PDBVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS7A2009PDBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input voltage supply, 1.6V to 6.0V; place capacitor as close as possible from IN to GND for best transient response and to minimize input impedance.
2 GND power_in Common ground reference.
3 EN input Enable input active high; output disabled when EN < VEN(LOW)=0.3V, enabled when EN > VEN(HI)=0.9V; features internal 500kΩ pulldown resistor.
4 N/C unconnected No internal electrical connection.
5 OUT power_out Regulated output voltage 0.8V to 5.5V with ±1.5% tolerance; requires low ESR capacitor from OUT to GND for stability; internal 150Ω pulldown resistor for discharge in shutdown mode.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

CAD (KiCad official)

  • Symbol: TPS7A2009PDBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps7a2009pdbvr-etched.step / tps7a2009pdbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7a2009pdbvr.step / tps7a2009pdbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (63 pp, sha256 f865f163779e6948, retrieved 2026-09-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF