component
TPS7A1633DGNR
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, HVSSOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS7A1633DGNR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HVSSOP-8-EP
TPS7A1633DGNR from Texas Instruments, in a HVSSOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulator output pin; a capacitor of at least 2.2 µF must be tied from this pin to ground to assure stability, with TI recommending a 10-µF ceramic capacitor to maximize AC performance. |
| 2 | FB/DNC | unconnected | For the fixed-voltage TPS7A1633 (3.3 V) version this pin must be left unconnected and not routed to any electrical net, not even GND or IN (on the adjustable version this pin is the error-amplifier feedback input). |
| 3 | PG | output | Power-good open-collector output; leave open or connect to GND if the power-good function is not needed, and it can be pulled up to any rail of 5 V or lower. |
| 4 | GND | power_in | Ground pin for the device. |
| 5 | EN | input | Enable pin that turns the regulator on when VEN ≥ VEN_HI and off when VEN ≤ VEN_LO; if unused, tie to IN, ensuring VEN never exceeds VIN. |
| 6 | NC | unconnected | No-connect pin that can be left open or tied to any voltage between GND and IN. |
| 7 | DELAY | output | Delay pin; connect a capacitor to GND to set the power-good delay time (charged by the internal DELAY pin current), or leave open if the reset/delay function is not needed. |
| 8 | IN | power_in | Regulator input supply pin; a capacitor of at least 0.1 µF must be tied from this pin to ground for stability, with TI recommending a 10-µF ceramic capacitor close to the device to reduce sensitivity to PCB layout. |
| 9 | PowerPAD | power_in | Exposed thermal pad that should be soldered to the PCB ground plane to enhance thermal performance; it can be left floating but TI highly recommends connecting it to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVSSOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
CAD (KiCad official)
- Symbol:
TPS7A1633DGNR - Footprint:
Package_SO:HVSSOP-8-1EP_3x3mm_P0.65mm_EP1.57x1.89mm - 3D model: HVSSOP-8-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.0 mm nominal HVSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps7a1633dgnr-etched.step/tps7a1633dgnr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a1633dgnr.step/tps7a1633dgnr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (37 pp, sha256
180ec3f485b2772b, retrieved 2026-10-01, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).