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TPS7A1112PDRVR

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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TPS7A1112PDRVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)

TPS7A1112PDRVR from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Regulated output pin capable of 500mA maximum output current; requires 2.2µF to 22µF ceramic capacitor (ESR < 250mΩ) to ground for stability.
2 NC unconnected No internal connection; may be connected to ground for improved thermal dissipation or left floating.
3 EN input Enable input (active high); device enables when EN > 0.9V and disables when EN < 0.4V.
4 BIAS power_in Bias power supply input with 1.7V to 5.5V operating range; requires 0.1µF ceramic capacitor to ground and exhibits 0.85V to 1.2V dropout voltage at 500mA output current.
5 GND power_in Ground return pin; must be connected to ground, and exposed thermal pad must be connected to large-area ground plane for thermal management.
6 IN power_in Input power supply pin with 0.75V to 3.3V operating range; requires 2.2µF ceramic capacitor to ground for stability and exhibits 90mV to 140mV dropout voltage at 500mA.
7 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-6-EP(2x2)
Category Power Management (PMIC)
Pins 7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN -0.3 3.6 V 5
Enable voltage VEN -0.3 6 V 5
Bias voltage VBIAS -0.3 6 V 5
Output voltage VOUT -0.3 V 5
Operating junction temperature TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
Input voltage VIN 0.75 3.3 V 5
Bias voltage VBIAS 1.7 5.5 V 5
Output voltage VOUT 0.5 3 V 5
Peak output current IOUT 0 500 mA 5
Input capacitor CIN 2.2 µF 5
Output capacitor COUT 2.2 22 µF Maximum ESR must be lower than 250 mΩ 5
Operating junction temperature TJ -40 125 °C 5
Nominal accuracy -0.5 0.5 % TJ = 25°C 6
Accuracy over temperature (DRV package) -1.25 1.25 % –20°C ≤ TJ ≤ 85°C, VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V, VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V, 1 mA ≤ IOUT ≤ 500 mA 6
Accuracy over temperature -1.5 1.5 % –40°C ≤ TJ ≤ 125°C, VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V, VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V, 1 mA ≤ IOUT ≤ 500 mA 6
Bias pin current IQ(BIAS) IQ(BIAS) 3 6 8 µA TJ = 25°C, IOUT = 0 mA 6
Bias pin current IQ(BIAS) IQ(BIAS) 11 µA –40°C < TJ < 85°C, IOUT = 0 mA 6
Bias pin current IQ(BIAS) IQ(BIAS) 14 µA IOUT = 0 mA 6
Bias pin current IQ(BIAS) IQ(BIAS) 60 µA IOUT = 500 mA 6
Input pin current IQ(IN) IQ(IN) 1.6 2.1 µA TJ = 25°C, IOUT = 0 mA 6
Input pin current IQ(IN) IQ(IN) 2.3 µA –40°C < TJ < 85°C, IOUT = 0 mA 6
Input pin current IQ(IN) IQ(IN) 2.6 µA IOUT = 0 mA 6
Input pin current IQ(IN) IQ(IN) 11 µA IOUT = 500 mA 6
VBIAS shutdown current ISHDN(BIAS) 400 nA –40°C < TJ < 85°C, VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V 6
VBIAS shutdown current ISHDN(BIAS) 1200 nA –40°C < TJ < 125°C, VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V 6
VIN shutdown current ISHDN(IN) 1 µA –40°C < TJ < 85°C, VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V 6
VIN shutdown current ISHDN(IN) 3 µA –40°C < TJ < 125°C, VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V 6
Output current limit ICL 700 990 1250 mA VOUT = 0.9 × VOUT(NOM), DRV package 7
Short circuit current limit ISC 300 mA VOUT = 0 V 7
VIN dropout voltage VDO(IN) 90 140 mV VIN = VOUT(NOM) – 0.1 V, IOUT = 500 mA, DRV package 7
VBIAS dropout voltage VDO(BIAS) 0.85 1.2 V IOUT = 500 mA 7
VBIAS dropout voltage VDO(BIAS) 0.75 1 V IOUT = 250 mA 7
Bias supply UVLO rising VUVLO(BIAS) 1.46 1.54 1.63 V VBIAS rising 7
Bias supply UVLO falling VUVLO(BIAS) 1.35 1.44 1.55 V VBIAS falling 7
Input supply UVLO rising VUVLO(IN) 645 675 710 mV VIN rising 7
Input supply UVLO falling VUVLO(IN) 565 600 640 mV VIN falling 7
Start-up time tSTR 525 1200 µs Time from EN assertion to 0.95 × VOUT(NOM) 7
EN pin logic high voltage VHI(EN) 0.9 V 7
EN pin logic low voltage VLO(EN) 0.4 V 7
EN pin current IEN 10 nA EN = 5.5 V 7
VIN line regulation ΔVOUT/ΔVIN 0.001 %/V VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V 6
VBIAS line regulation ΔVOUT/ΔVBIAS 0.03 %/V VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V 6
Load regulation ΔVOUT/ΔIOUT 0.2 %/A 0.1 mA ≤ IOUT ≤ 500 mA 6
VIN power-supply rejection ratio VIN PSRR 64 dB f = 1 kHz, VOUT = 1.0 V, IOUT = 50 mA 7
VIN power-supply rejection ratio VIN PSRR 37 dB f = 100 kHz, VOUT = 1.0 V, IOUT = 50 mA 7
VIN power-supply rejection ratio VIN PSRR 31 dB f = 1 MHz, VOUT = 1.0 V, IOUT = 50 mA 7
VIN power-supply rejection ratio VIN PSRR 35 dB f = 1.5 MHz, VOUT = 1.0 V, IOUT = 50 mA 7
VBIAS power-supply rejection ratio VBIAS PSRR 56 dB f = 1 kHz, VOUT = 1.0 V, IOUT = 500 mA 7
VBIAS power-supply rejection ratio VBIAS PSRR 43 dB f = 100 kHz, VOUT = 1.0 V, IOUT = 500 mA 7
VBIAS power-supply rejection ratio VBIAS PSRR 33 dB f = 1 MHz, VOUT = 1.0 V, IOUT = 500 mA 7
Output voltage noise Vn 93.9 µVRMS Bandwidth = 10 Hz to 100 kHz, VOUT = 1.0 V, IOUT = 50 mA 7
Bias supply hysteresis VUVLO_HYST(BIAS) 80 mV VBIAS hysteresis 7
Input supply hysteresis VUVLO_HYST(IN) 75 mV VIN hysteresis 7
Pulldown resistor RPULLDOWN 120 Ω VBIAS = 3.3 V, P version only 7
Thermal shutdown temperature (shutdown, rising) TSD 160 °C Shutdown, temperature rising 7
Thermal shutdown temperature (reset, falling) TSD 145 °C Reset, temperature falling 7
Bias capacitor CBIAS 0.1 µF 5
Junction-to-ambient thermal resistance (DRV) RθJA 77.3 °C/W DRV (WSON) package 6
Junction-to-case (bottom) thermal resistance (DRV) RθJC(bot) 18.6 °C/W DRV (WSON) package 6

CAD (KiCad official)

  • Symbol: TPS7A1112PDRVR
  • Footprint: Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
  • 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: tps7a1112pdrvr-etched.step / tps7a1112pdrvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7a1112pdrvr.step / tps7a1112pdrvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (42 pp, sha256 d60d50d243fb0861, retrieved 2026-09-24, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF