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TPS7A11105PDRVR
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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownTPS7A11105PDRVR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)
TPS7A11105PDRVR from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Regulated output pin that requires a capacitor from OUT to ground for stability, with COUT of 2.2 µF to 22 µF and ESR below 250 mΩ. |
| 2 | NC | unconnected | Not internally connected; connect to ground for better thermal dissipation or leave floating. |
| 3 | EN | input | Enable pin: logic high enables the device and logic low disables it, and connecting EN to IN is only acceptable if the IN pin voltage is greater than 0.9 V. |
| 4 | BIAS | input | Bias pin that enables low-input, low-output voltage operation, with a recommended bias capacitor of 0.1 µF and a VBIAS range of 1.7 V to 5.5 V. |
| 5 | GND | power_in | Ground pin that must be connected to ground. |
| 6 | IN | input | Input pin that requires a capacitor from IN to ground (CIN of 2.2 µF minimum), with a VIN range of 0.75 V to 3.3 V. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6-EP(2x2) |
| Category | Power Management (PMIC) |
| Pins | 7 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal accuracy | -0.5 | 0.5 | % | TJ = 25°C | 6 | ||
| Accuracy over temperature | -1.25 | 1.25 | % | -20°C ≤ TJ ≤ 85, DRV package, VOUT(NOM)+0.5 V ≤ VIN ≤ 3.3 V, VOUT(NOM)+1.4 V ≤ VBIAS ≤ 5.5 V, 1 mA ≤ IOUT ≤ 500 mA | 6 | ||
| Accuracy over temperature | -1.5 | 1.5 | % | -40°C ≤ TJ ≤ 125, VOUT(NOM)+0.5 V ≤ VIN ≤ 3.3 V, VOUT(NOM)+1.4 V ≤ VBIAS ≤ 5.5 V, 1 mA ≤ IOUT ≤ 500 mA | 6 | ||
| VIN line regulation | ΔVOUT/ΔVIN | 0.001 | %/V | VOUT(NOM)+0.5 V ≤ VIN ≤ 3.3 V | 6 | ||
| VBIAS line regulation | ΔVOUT/ΔVBIAS | 0.03 | %/V | VOUT(NOM)+1.4 V ≤ VBIAS ≤ 5.5 V | 6 | ||
| Load regulation | ΔVOUT/ΔIOUT | 0.2 | %/A | 0.1 mA ≤ IOUT ≤ 500 mA | 6 | ||
| Bias pin current | IQ(BIAS) | 3 | 6 | 8 | µA | TJ = 25°C, IOUT = 0 mA | 6 |
| Bias pin current | IQ(BIAS) | 11 | µA | -40°C < TJ < 85°C, IOUT = 0 mA | 6 | ||
| Bias pin current | IQ(BIAS) | 14 | µA | IOUT = 0 mA | 6 | ||
| Bias pin current | IQ(BIAS) | 60 | µA | IOUT = 500 mA | 6 | ||
| Input pin current | IQ(IN) | 1.6 | 2.1 | µA | TJ = 25°C, IOUT = 0 mA | 6 | |
| Input pin current | IQ(IN) | 2.3 | µA | -40°C < TJ < 85°C, IOUT = 0 mA | 6 | ||
| Input pin current | IQ(IN) | 2.6 | µA | IOUT = 0 mA | 6 | ||
| Input pin current | IQ(IN) | 11 | µA | IOUT = 500 mA | 6 | ||
| VBIAS shutdown current | ISHDN(BIAS) | 400 | nA | -40°C < TJ < 85°C, VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V | 6 | ||
| VBIAS shutdown current | ISHDN(BIAS) | 1200 | nA | -40°C < TJ < 125°C, VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V | 6 | ||
| VIN shutdown current | ISHDN(IN) | 1 | µA | -40°C < TJ < 85°C, VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V | 6 | ||
| VIN shutdown current | ISHDN(IN) | 3 | µA | -40°C < TJ < 125°C, VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V | 6 | ||
| Output current limit | ICL | 700 | 990 | 1250 | mA | VOUT = 0.9 × VOUT(NOM), DRV Package | 6 |
| Short circuit current limit | ISC | 300 | mA | VOUT = 0 V | 7 | ||
| VIN dropout voltage | VDO(IN) | 90 | 140 | mV | VIN = VOUT(NOM), 0.1 V, IOUT = 500 mA, DRV package | 7 | |
| VBIAS dropout voltage | VDO(BIAS) | 0.85 | 1.2 | V | IOUT = 500 mA | 7 | |
| VBIAS dropout voltage | VDO(BIAS) | 0.75 | 1 | V | IOUT = 250 mA | 7 | |
| VIN power-supply rejection ratio | VIN PSRR | 64 | dB | f = 1 kHz, VOUT = 1.0 V, IOUT = 50 mA | 7 | ||
| VIN power-supply rejection ratio | VIN PSRR | 37 | dB | f = 100 kHz, VOUT = 1.0 V, IOUT = 50 mA | 7 | ||
| VIN power-supply rejection ratio | VIN PSRR | 31 | dB | f = 1 MHz, VOUT = 1.0 V, IOUT = 50 mA | 7 | ||
| VIN power-supply rejection ratio | VIN PSRR | 35 | dB | f = 1.5 MHz, VOUT = 1.0 V, IOUT = 50 mA | 7 | ||
| VBIAS power-supply rejection ratio | VBIAS PSRR | 56 | dB | f = 1 kHz, VOUT = 1.0 V, IOUT = 500 mA | 7 | ||
| VBIAS power-supply rejection ratio | VBIAS PSRR | 43 | dB | f = 100 kHz, VOUT = 1.0 V, IOUT = 500 mA | 7 | ||
| VBIAS power-supply rejection ratio | VBIAS PSRR | 33 | dB | f = 1 MHz, VOUT = 1.0 V, IOUT = 500 mA | 7 | ||
| Output voltage noise | Vn | 93.9 | µVRMS | Bandwidth = 10 Hz to 100 kHz, VOUT = 1.0 V, IOUT = 50 mA | 7 | ||
| Bias supply UVLO rising | VUVLO(BIAS) | 1.46 | 1.54 | 1.63 | V | VBIAS rising | 7 |
| Bias supply UVLO falling | VUVLO(BIAS) | 1.35 | 1.44 | 1.55 | V | VBIAS falling | 7 |
| Bias supply hysteresis | VUVLO_HYST(BIAS) | 80 | mV | VBIAS hysteresis | 7 | ||
| Input supply UVLO rising | VUVLO(IN) | 645 | 675 | 710 | mV | VIN rising | 7 |
| Input supply UVLO falling | VUVLO(IN) | 565 | 600 | 640 | mV | VIN falling | 7 |
| Input supply hysteresis | VUVLO_HYST(IN) | 75 | mV | VIN hysteresis | 7 | ||
| Start-up time | tSTR | 525 | 1200 | µs | 7 | ||
| EN pin logic high voltage | VHI(EN) | 0.9 | V | 7 | |||
| EN pin logic low voltage | VLO(EN) | 0.4 | V | 7 | |||
| EN pin current | IEN | 10 | nA | EN = 5.5 V | 7 | ||
| Pulldown resistor | RPULLDOWN | 120 | Ω | VBIAS = 3.3 V, P version only | 7 | ||
| Thermal shutdown temperature, shutdown | TSD | 160 | °C | Shutdown, temperature rising | 7 | ||
| Thermal shutdown temperature, reset | TSD | 145 | °C | Reset, temperature falling | 7 | ||
| Input voltage | VIN | -0.3 | 3.6 | V | 5 | ||
| Enable voltage | VEN | -0.3 | 6 | V | 5 | ||
| Bias voltage | VBIAS | -0.3 | 6 | V | 5 | ||
| Output voltage | VOUT | -0.3 | V | Maximum VIN + 0.3 V (absolute maximum 3.6 V or VIN + 0.3 V, whichever is less) | 5 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| Input voltage | VIN | 0.75 | 3.3 | V | 5 | ||
| Bias voltage | VBIAS | 1.7 | 5.5 | V | 5 | ||
| Output voltage | VOUT | 0.5 | 3 | V | 5 | ||
| Peak output current | IOUT | 0 | 500 | mA | 5 | ||
| Input capacitor | CIN | 2.2 | µF | 5 | |||
| Bias capacitor | CBIAS | 0.1 | µF | 5 | |||
| Output capacitor | COUT | 2.2 | 22 | µF | Maximum ESR must be lower than 250 mΩ | 5 | |
| Operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| Junction-to-ambient thermal resistance, DRV (WSON) | RθJA | 77.3 | °C/W | DRV (WSON) 6 pins | 6 | ||
| Junction-to-case (top) thermal resistance, DRV (WSON) | RθJC(top) | 91.6 | °C/W | DRV (WSON) 6 pins | 6 | ||
| Junction-to-board thermal resistance, DRV (WSON) | RθJB | 41.1 | °C/W | DRV (WSON) 6 pins | 6 | ||
| Junction-to-top characterization parameter, DRV (WSON) | ψJT | 4.3 | °C/W | DRV (WSON) 6 pins | 6 | ||
| Junction-to-board characterization parameter, DRV (WSON) | ψJB | 41 | °C/W | DRV (WSON) 6 pins | 6 | ||
| Junction-to-case (bottom) thermal resistance, DRV (WSON) | RθJC(bot) | 18.6 | °C/W | DRV (WSON) 6 pins | 6 |
CAD (KiCad official)
- Symbol:
TPS7A11105PDRVR - Footprint:
Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm - 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
tps7a11105pdrvr-etched.step/tps7a11105pdrvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a11105pdrvr.step/tps7a11105pdrvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (41 pp, sha256
af774819c7eef8dd, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).