component

TPS7A0323PDBVR

Public Made by Adom

by adom

Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps7a0323pdbvrfactory-2.0.0extractor-text

Verified TPS7A0323PDBVR

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 5 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS7A0323PDBVR · SOT-23-5 · 5 pins
  • ✓copper: 5 copper pads, none touching another net
  • ✓datasheet: all 5 pin names found in the 52-page datasheet
  • ✓distributor: lcsc C3746275, digikey 296-TPS7A0323PDBVRTR-ND, mouser 595-TPS7A0323PDBVR
  • ✓family: SOT-23-5
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-8ddd9tul/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 5 pins = 5 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 5 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps7a0323pdbvr.kicad_sym✓ tps7a0323pdbvr.kicad_mod✓ tps7a0323pdbvr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 16h ago
viewers tps7a0323pdbvr: viewers · Ray 16h ago
package.json Publish 0.1.0 · Ray 16h ago
page.json Set visibility: public · Ray 16h ago
README.md Publish 0.1.0 · Ray 16h ago
tps7a0323pdbvr-etched.glb Publish 0.1.0 · Ray 16h ago
tps7a0323pdbvr-etched.step tps7a0323pdbvr: factory component page (tier=mfr) · Ray 16h ago
tps7a0323pdbvr-hero.glb tps7a0323pdbvr: hero GLB from the etched model (keeps the MPN mark) · Ray 16h ago
tps7a0323pdbvr-hero.overlay.json Publish 0.1.0 · Ray 16h ago
tps7a0323pdbvr.glb Publish 0.1.0 · Ray 16h ago
tps7a0323pdbvr.kicad_mod Publish 0.1.0 · Ray 16h ago
tps7a0323pdbvr.kicad_sym Publish 0.1.0 · Ray 16h ago
tps7a0323pdbvr.lbr Publish 0.1.0 · Ray 16h ago
tps7a0323pdbvr.step Publish 0.1.0 · Ray 16h ago
verification.json Verified: Published by the parts factory: tier mfr, 5 pins · Ray 16h ago

TPS7A0323PDBVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS7A0323PDBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN input Input pin; use the recommended ceramic input capacitor value or larger from IN to ground, placed as close to the device as possible, with input voltage range 1.5 V to 6.0 V.
2 GND power_in Ground pin; connect to ground on the board.
3 EN input Enable pin; logic high enables the device, while logic low or floating disables it, with enable voltage rated 0 V to 6.0 V and an internal pulldown resistor.
4 NC unconnected No connect pin, not internally connected; connect to ground or leave floating.
5 OUT power_out Regulated output pin requiring an effective capacitance of 0.5 µF or greater from OUT to ground for stability, with a 1 µF or larger ceramic capacitor recommended for best transient response.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage accuracy over temperature -1.5 1.5 % VOUT ≥ 1.5 V, TJ = -40°C to +125°C 6
Nominal accuracy -1 1 % TJ = 25°C, VOUT ≥ 1.5 V, 1 µA ≤ IOUT ≤ 1 mA 6
Line regulation ΔVOUT(ΔVIN) 5 mV VOUT(nom) + 0.5 V ≤ VIN ≤ 6.0 V, TJ = -40°C to +125°C 6
Load regulation ΔVOUT(ΔIOUT) 20 38 mV 1 mA ≤ IOUT ≤ 200 mA, VIN = VOUT(nom) + 0.5 V, TJ = -40°C to +85°C 6
Load regulation ΔVOUT(ΔIOUT) 50 mV 1 mA ≤ IOUT ≤ 200 mA, VIN = VOUT(nom) + 0.5 V, TJ = -40°C to +125°C 6
Ground current IGND 200 250 nA IOUT = 0 mA, TJ = 25°C 6
Ground current IGND 300 nA IOUT = 0 mA, TJ = -40°C to +85°C 6
Ground current vs load current IGND/IOUT 1 % 20 µA ≤ IOUT < 1 mA, TJ = 25°C 6
Ground current vs load current IGND/IOUT 0.25 % 1 mA ≤ IOUT ≤ 100 mA, TJ = 25°C 6
Ground current vs load current IGND/IOUT 0.15 % IOUT ≥ 100 mA, TJ = 25°C 6
Ground current in dropout IGND(DO) 220 nA IOUT = 0 mA, VIN = 95% x VOUT (NOM), TJ = 25°C 6
Shutdown current ISHDN 3 10 nA VEN = 0 V, 1.5 V ≤ VIN ≤ 5.0 V, TJ = 25°C 6
Output current limit ICL 240 450 750 mA VOUT = 90% × VOUT(nom), VOUT < 2.5 V, VIN = VOUT(nom) + VDO(max) + 1.0 V 6
Short-circuit current limit ISC 65 mA VOUT = 0 V 6
Dropout voltage VDO 400 mV 1.8 V ≤ VOUT < 2.5 V, TJ = -40°C to +85°C, IOUT = 200 mA 6
Dropout voltage VDO 450 mV 1.8 V ≤ VOUT < 2.5 V, TJ = -40°C to +125°C, IOUT = 200 mA 6
Power-supply rejection ratio PSRR 55 dB f = 1 kHz, IOUT = 30 mA 6
UVLO threshold, VIN rising VUVLO 1.23 1.3 1.47 V VIN rising 6
UVLO threshold, VIN falling VUVLO 1 1.12 1.41 V VIN falling 6
UVLO hysteresis VUVLO(HYST) 180 mV VIN hysteresis 6
EN pin logic high voltage VEN(HI) 1.1 V 7
EN pin logic low voltage VEN(LOW) 0.3 V 7
EN pin leakage current IEN 10 nA VEN = VIN = 6.0 V 7
Smart enable pulldown resistor REN(PULLDOWN) 500 KΩ VEN = 0.3 V 7
Pulldown resistor RPULLDOWN 60 Ω VIN = 3.3 V, device disabled 7
Thermal shutdown temperature TSD(shutdown) 170 °C Shutdown, temperature increasing 7
Thermal shutdown reset temperature TSD(reset) 145 °C Reset, temperature decreasing 7
Start-up time tSTR 750 1200 µs From EN assertion to VOUT = 90% × VOUT(nom), 1.5 V < VOUT ≤ 3.0 V 7
Input voltage (absolute maximum) VIN -0.3 6.5 V 4
Enable voltage (absolute maximum) VEN -0.3 6.5 V 4
Output voltage (absolute maximum) VOUT -0.3 V Maximum is VIN + 0.3 V or 5.5 V, whichever is smaller 4
Operating junction temperature (absolute maximum) TJ -40 150 °C Operating junction 4
Storage temperature (absolute maximum) Tstg -65 150 °C Storage 4
Input voltage VIN 1.5 6 V 5
Enable voltage VEN 0 6 V 5
Output voltage VOUT 0.8 5 V 5
Output current IOUT 0 200 mA 5
Input capacitor CIN 1 µF 5
Output capacitor COUT 1 1 22 µF Footnotes: 0.5 µF effective minimum for stability; 22 µF maximum derated 5
EN toggle frequency FEN 10 kHz 5
Operating junction temperature TJ -40 125 °C 5
Junction-to-ambient thermal resistance RθJA 181.9 °C/W DBV (SOT-23-5) 5
Junction-to-case (top) thermal resistance RθJC(top) 53 °C/W DBV (SOT-23-5) 5
Junction-to-board thermal resistance RθJB 88.1 °C/W DBV (SOT-23-5) 5
Junction-to-top characterization parameter ψJT 27.1 °C/W DBV (SOT-23-5) 5
Junction-to-board characterization parameter ψJB 52.7 °C/W DBV (SOT-23-5) 5

CAD (KiCad official)

  • Symbol: TPS7A0323PDBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps7a0323pdbvr-etched.step / tps7a0323pdbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7a0323pdbvr.step / tps7a0323pdbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (52 pp, sha256 f477be5dcb30b388, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF