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TPS7A0230PDBVR

Public Made by Adom

by adom

Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs tps7a0230pdbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json tps7a0230pdbvr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC b… · Ray
README.md tps7a0230pdbvr: specified limits as data (metadata.characteristics, 46 rows from the datasheet) · Ray
tps7a0230pdbvr-etched.fit.json tps7a0230pdbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
tps7a0230pdbvr-etched.glb tps7a0230pdbvr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC b… · Ray
tps7a0230pdbvr-etched.step tps7a0230pdbvr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC b… · Ray
tps7a0230pdbvr.glb Publish 0.1.0 · Ray
tps7a0230pdbvr.kicad_mod Publish 0.1.0 · Ray
tps7a0230pdbvr.kicad_sym Publish 0.1.0 · Ray
tps7a0230pdbvr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
tps7a0230pdbvr.step Publish 0.1.0 · Ray

TPS7A0230PDBVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS7A0230PDBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Regulator input supply, 1.5 V to 6.0 V. Place a 1-µF (or larger) ceramic input capacitor from IN to GND, as close to the pin as possible, to minimize input impedance and improve transient response.
2 GND power_in Device ground. Must be connected to the board ground plane; serves as the return path for the LDO and reference.
3 EN input Active-high enable input (V_EN(HI) ≥ 1.1 V, V_EN(LOW) ≤ 0.3 V). Drive high to enable the regulator, low or float to disable. Integrates a smart pulldown (~500 kΩ, disconnected after startup) so the pin may be floated. V_EN range 0 to 6.0 V.
4 NC unconnected No internal connection. Tie to ground or leave floating.
5 OUT power_out Regulated output, fixed 3.0 V, up to 200 mA. Requires a minimum 0.5-µF effective output capacitance for stability; a 1-µF (up to 22 µF derated) ceramic to GND is recommended for best transient response. Place close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category PMIC
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • TPS7A0230PDBVR
  • TPS7A0230PDBVRDBVT
  • TPS7A0230PDBVRDQNR
  • TPS7A0230PDBVRYCHR

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Nominal output accuracy -1 1 % TJ = 25°C, VOUT ≥ 1.5 V, 1 µA ≤ IOUT ≤ 1 mA 6
Accuracy over temperature -1.5 1.5 % VOUT ≥ 1.5 V, TJ = –40°C to +125°C 6
Line regulation ΔVOUT(ΔVIN) 5 mV VOUT(nom) + 0.5 V ≤ VIN ≤ 6.0 V, TJ = –40°C to +125°C 6
Load regulation ΔVOUT(ΔIOUT) 20 38 mV 1 mA ≤ IOUT ≤ 200 mA, VIN = VOUT(nom) + 0.5 V, TJ = –40°C to +85°C 6
Load regulation ΔVOUT(ΔIOUT) 50 mV 1 mA ≤ IOUT ≤ 200 mA, VIN = VOUT(nom) + 0.5 V, TJ = –40°C to +125°C 6
Ground current IGND 25 46 nA IOUT = 0 mA, TJ = 25°C 6
Ground current IGND 60 nA IOUT = 0 mA, TJ = –40°C to +85°C 6
Ground current vs load current IGND/IOUT 1 % 5 µA ≤ IOUT < 1 mA, TJ = 25°C 6
Ground current vs load current IGND/IOUT 0.25 % 1 mA ≤ IOUT < 100 mA, TJ = 25°C 6
Ground current vs load current IGND/IOUT 0.15 % IOUT ≥ 100 mA, TJ = 25°C 6
Ground current in dropout IGND(DO) 25 nA IOUT = 0 mA, VIN = 95% x VOUT(NOM), TJ = 25°C 6
Shutdown current ISHDN 3 10 nA VEN = 0 V, 1.5 V ≤ VIN ≤ 5.0 V, TJ = 25°C 6
Output current limit ICL 240 450 750 mA VOUT = 90% × VOUT(nom), VOUT ≥ 2.5 V, VIN = VOUT(nom) + VDO(max) + 0.5 V 6
Short-circuit current limit ISC 65 mA VOUT = 0 V 6
Dropout voltage VDO 310 mV TJ = –40°C to +85°C, 2.5 V ≤ VOUT < 3.3 V 6
Dropout voltage VDO 360 mV TJ = –40°C to +125°C, 2.5 V ≤ VOUT < 3.3 V 6
Power-supply rejection ratio PSRR 55 dB f = 1 kHz, IOUT = 30 mA 6
UVLO threshold, VIN rising VUVLO 1.23 1.3 1.47 V VIN rising 6
UVLO threshold, VIN falling VUVLO 1 1.12 1.41 V VIN falling 6
UVLO hysteresis VUVLO(HYST) 180 mV VIN hysteresis 7
EN pin logic high voltage VEN(HI) 1.1 V 7
EN pin logic low voltage VEN(LOW) 0.3 V 7
EN pin leakage current IEN 10 nA VEN = VIN = 6.0 V 7
Smart enable pulldown resistor REN(PULLDOWN) 500 KΩ VEN = 0.3 V 7
Pulldown resistor RPULLDOWN 60 Ω VIN = 3.3 V, device disabled 7
Thermal shutdown temperature TSD(shutdown) 170 °C Shutdown, temperature increasing 7
Thermal shutdown reset temperature TSD(reset) 145 °C Reset, temperature decreasing 7
Start-up time tSTR 750 1200 µs 1.5 V < VOUT ≤ 3.0 V, from EN assertion to VOUT = 90% × VOUT(nom) 7
Input voltage VIN 1.5 6 V 5
Enable voltage VEN 0 6 V 5
Output voltage VOUT 0.8 5 V 5
Output current IOUT 0 200 mA 5
Input capacitor CIN 1 µF 5
Output capacitor COUT 1 1 22 µF Effective output capacitance of 0.5 µF minimum required for stability; 22 µF is maximum derated capacitance 5
EN toggle frequency FEN 10 kHz 5
Operating junction temperature TJ -40 125 °C 5
Input voltage VIN -0.3 6.5 V 4
Enable voltage VEN -0.3 6.5 V 4
Output voltage VOUT -0.3 V Maximum is VIN + 0.3 V or 5.5 V, whichever is smaller 4
Operating junction temperature TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
Junction-to-ambient thermal resistance (DBV) RθJA 181.9 °C/W 5
Junction-to-case (top) thermal resistance (DBV) RθJC(top) 53 °C/W 5
Junction-to-board thermal resistance (DBV) RθJB 88.1 °C/W 5
Junction-to-top characterization parameter (DBV) ψJT 27.1 °C/W 5
Junction-to-board characterization parameter (DBV) ψJB 52.7 °C/W 5

CAD (KiCad official)

  • Symbol: TPS7A0230PDBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps7a0230pdbvr-etched.step / tps7a0230pdbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7a0230pdbvr.step / tps7a0230pdbvr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tps7a0230pdbvr.step 85 KB You want the bare part, or you mark your own boards.
tps7a0230pdbvr-etched.step 2.6 MB You want the part with TPS7A0230PDBVR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 629 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (47 pp, sha256 df784ba192d0a660, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF