# TPS79650DCQR

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-223-6

TPS79650DCQR from Texas Instruments, in a SOT-223-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable pin: driving EN high turns on the regulator, driving it low puts the regulator into shutdown, and EN can be connected to IN if not used. |
| 2 | IN | power_in | Input to the device. |
| 3 | GND | power_in | Regulator ground. |
| 4 | OUT | power_out | Output of the regulator. |
| 5 | NR/NC | passive | On the legacy chip this is the noise-reduction pin, where an external capacitor bypasses internal band-gap noise to improve PSRR and reduce output noise; on the new chip it is not internally connected and must be left open or tied to GND. |
| 6 | GND | power_in | Tab of the SOT-223 package, regulator ground, same net as pin 3. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-223-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output accuracy (fixed VOUT = 5V) | VOUT | -3 |  | 3 | % | 0 µA ≤ IOUT ≤ 1A, VOUT(nom) + 1V ≤ VIN ≤ 5.5V | 6 |
| Input supply voltage (legacy chip) | VIN | 2.7 |  | 5.5 | V |  | 5 |
| Input supply voltage (new chip) | VIN | 2.7 |  | 6 | V |  | 5 |
| Output current | IOUT | 0 |  | 1 | A |  | 5 |
| Enable voltage (legacy chip) | VEN | 0 |  | 5.5 | V |  | 5 |
| Enable voltage (new chip) | VEN | 0 |  | 6 | V |  | 5 |
| Junction temperature | Tj | -40 |  | 125 | °C |  | 5 |
| Output capacitor | COUT | 1 |  | 200 | µF |  | 5 |
| Feed-forward capacitor (new chip) | CFF | 0 | 10 | 100 | nF |  | 5 |
| Supply voltage (new chip) | VIN | -0.3 |  | 6.5 | V |  | 4 |
| Supply voltage (legacy chip) | VIN | -0.3 |  | 6 | V |  | 4 |
| Output voltage | VOUT | -0.3 |  | 6 | V |  | 4 |
| Enable voltage | VEN | -0.3 |  |  | V | maximum VIN + 0.3 | 4 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Electrostatic discharge, human body model | V(ESD) | -2000 |  | 2000 | V | Human body model (HBM), all pins | 4 |
| Electrostatic discharge, charged device model | V(ESD) | -500 |  | 500 | V | Charged device model (CDM), all pins | 4 |
| Dropout voltage (TPS79650) | VDO |  | 220 | 300 | mV | IOUT = 1A | 6 |
| Line regulation | ΔVOUT/ΔVIN |  | 0.05 | 0.12 | %/V | VOUT + 1V ≤ VIN ≤ 5.5V | 6 |
| Ground current (legacy chip) | IGND |  | 265 | 385 | µA | 0µA ≤ IOUT ≤ 1A (legacy chip) | 6 |
| Ground current (new chip) | IGND |  | 700 | 1100 | µA | 0µA ≤ IOUT ≤ 1A (new chip) | 6 |
| Output current limit (legacy chip) | ICL | 2.4 |  | 4.2 | A | VOUT = 0 (legacy chip) | 6 |
| Output current limit (new chip) | ICL | 1.04 |  | 1.65 | A | VIN = VOUT(nom) + 1.25V or 2.0V (whichever is greater), VOUT = 0.9x VOUT(nom) (new chip only) | 6 |
| Shutdown current | ISHDN |  | 0.07 | 1 | µA | VEN = 0V, 2.7 V ≤ VIN ≤ 5.5V | 6 |
| Enable pin current | IEN | -1 |  | 1 | µA | VEN = 0V | 7 |
| UVLO threshold, VIN rising (legacy chip) | VUVLO |  | 2.25 | 2.65 | V | VIN rising (legacy chip) | 7 |
| UVLO threshold, VIN rising (new chip) | VUVLO |  | 1.28 | 1.62 | V | VIN rising (new chip) | 7 |
| Junction-to-ambient thermal resistance (DCQ, legacy chip) | RθJA |  | 70.4 |  | °C/W | DCQ (SOT223-6), 6 pins, legacy chip | 5 |
| Junction-to-ambient thermal resistance (DCQ, new chip) | RθJA |  | 71.1 |  | °C/W | DCQ (SOT223-6), 6 pins, new chip | 5 |
| Junction-to-case (top) thermal resistance (DCQ, legacy chip) | RθJC(top) |  | 70 |  | °C/W | DCQ (SOT223-6), 6 pins, legacy chip | 5 |
| Junction-to-case (top) thermal resistance (DCQ, new chip) | RθJC(top) |  | 41.6 |  | °C/W | DCQ (SOT223-6), 6 pins, new chip | 5 |
| Junction-to-case (bottom) thermal resistance (DCQ, legacy chip) | RθJC(bot) |  | 6.3 |  | °C/W | DCQ (SOT223-6), 6 pins, legacy chip | 5 |
| Junction-to-case (bottom) thermal resistance (DCQ, new chip) | RθJC(bot) |  | 6 |  | °C/W | DCQ (SOT223-6), 6 pins, new chip | 5 |

## CAD (KiCad official)

- Symbol: `TPS79650DCQR`
- Footprint: `Package_TO_SOT_SMD:SOT-223-6`
- 3D model: SOT-223-6 (KiCad packages3D, STEP)
- 3D model files: `tps79650dcqr-etched.step` / `tps79650dcqr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps79650dcqr.step` / `tps79650dcqr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps796.pdf) (50 pp, sha256 `c1deafb8b70d6ac9`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps79650dcqr-datasheet.pdf)