component
TPS79428DCQR
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-223-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
Ray
tps79428dcqr: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S…
6247934
17d ago
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{
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"type": "component",
"description": "Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-223-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"power management (pmic)",
"tps79428dcqr",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"tps79428dcqr.kicad_sym",
"tps79428dcqr.kicad_mod",
"tps79428dcqr.glb",
"tps79428dcqr.step",
"tps79428dcqr.lbr",
"docs/hero.png",
"docs/tps79428dcqr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"tps79428dcqr-hero.glb",
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"component": {
"mpn": "TPS79428DCQR",
"manufacturer": "Texas Instruments",
"package": "SOT-223-6",
"pin_count": 6,
"category": "Power Management (PMIC)",
"subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",
"datasheet": "https://www.ti.com/cn/lit/gpn/tps794",
"parts": {
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"footprint": "tps79428dcqr.kicad_mod",
"model_3d": "tps79428dcqr-hero.glb",
"model_3d_plain": "tps79428dcqr.glb",
"model_3d_step": "tps79428dcqr-etched.step",
"model_3d_step_plain": "tps79428dcqr.step",
"lbr": "tps79428dcqr.lbr"
},
"distributor_links": {
"lcsc": "C2877949",
"digikey": "296-TPS79428DCQRTR-ND",
"mouser": "595-TPS79428DCQR"
},
"distributor_check": {
"checked_at": "2026-10-11T22:52:53Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "296-TPS79428DCQRTR-ND",
"status": "found",
"lifecycle": "Active"
},
"mouser": {
"pn": "595-TPS79428DCQR",
"status": "found"
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},
"pins": [
{
"number": "1",
"name": "EN",
"type": "input",
"description": "Enable input: a logic-high level enables the device and a logic-low level (below VEN(LOW), max 0.7 V for the old chip or 0.425 V for the new chip) puts it in shutdown, with VEN(HI) of at least 1.7 V (old chip) or 0.85 × VIN (new chip) and VEN up to 5.5 V."
},
{
"number": "2",
"name": "IN",
"type": "input",
"description": "Unregulated input to the regulator, operating over 2.7 V to 5.5 V, with an absolute maximum of 6 V (old chip) or VIN + 0.3 V / 6.5 V, whichever is smaller (new chip), and a ceramic input bypass capacitor of at least 1 µF to GND."
},
{
"number": "3",
"name": "GND",
"type": "power_in",
"description": "Regulator ground, which should connect directly to the bypass-capacitor grounds and be kept on its own ground plane for best PSRR and noise performance."
},
{
"number": "4",
"name": "OUT",
"type": "output",
"description": "Regulator output, which requires a ceramic output capacitor of at least 1 µF (recommended 2.2 µF, with a minimum effective 0.47 µF on the new chip) between OUT and GND for loop stability."
},
{
"number": "5",
"name": "NR/NC",
"type": "input",
"description": "On the old chip this is the noise-reduction pin, where an external capacitor of 0 to 100 nF (CNR, which must have minimal leakage) filters bandgap noise; on the new chip it is a no-connect pin that should be tied to GND or left floating."
},
{
"number": "6",
"name": "GND",
"type": "power_in",
"description": "Ground pin that is also electrically tied to the SOT-223 thermal tab, which must be soldered to a large copper area on the board to dissipate heat."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pin 5 is listed as 'input (old chip) / no connect (new chip)' in the pin table, so the ERC type 'inp; Conflicting statements on NR availability for DCQ: Figure 4-2 and Table 4-1 give pin 5 as NR/FB/NC f; The DCQ GND pin numbers (3 and 6) are read from the table row 'GND 5, PAD 3、6' by column position; t"
],
"pages_sent": 24,
"cost_usd": 0.1048,
"at": "2026-10-11T22:52:40"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/tps794",
"pages": 51,
"sha256": "84291eb77a7c37c6",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 6,
"described": 6,
"cites_pages": true,
"refuses_to_fabricate": true
}
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"sha256": "bf43e0f52215e5c8b069c660d1a580928edb1037d7f7155d98bb6d1df79e64ff",
"checked": "2026-10-11",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "tps79428dcqr-etched.step",
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"sha256": "792013391ab3dcb19a2f2b4f5315cf723b66938aa1fd3c4f4a65c44b6587d01f",
"checked": "2026-10-16",
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}
}