TPS79428DCQR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-223-6

TPS79428DCQR from Texas Instruments, in a SOT-223-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	EN	input	Enable input: a logic-high level enables the device and a logic-low level (below VEN(LOW), max 0.7 V for the old chip or 0.425 V for the new chip) puts it in shutdown, with VEN(HI) of at least 1.7 V (old chip) or 0.85 × VIN (new chip) and VEN up to 5.5 V.
2	IN	input	Unregulated input to the regulator, operating over 2.7 V to 5.5 V, with an absolute maximum of 6 V (old chip) or VIN + 0.3 V / 6.5 V, whichever is smaller (new chip), and a ceramic input bypass capacitor of at least 1 µF to GND.
3	GND	power_in	Regulator ground, which should connect directly to the bypass-capacitor grounds and be kept on its own ground plane for best PSRR and noise performance.
4	OUT	output	Regulator output, which requires a ceramic output capacitor of at least 1 µF (recommended 2.2 µF, with a minimum effective 0.47 µF on the new chip) between OUT and GND for loop stability.
5	NR/NC	input	On the old chip this is the noise-reduction pin, where an external capacitor of 0 to 100 nF (CNR, which must have minimal leakage) filters bandgap noise; on the new chip it is a no-connect pin that should be tied to GND or left floating.
6	GND	power_in	Ground pin that is also electrically tied to the SOT-223 thermal tab, which must be soldered to a large copper area on the board to dissipate heat.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOT-223-6
Category	Power Management (PMIC)
Pins	6

CAD (KiCad official)

Symbol: TPS79428DCQR
Footprint: Package_TO_SOT_SMD:SOT-223-6
3D model: SOT-223-6 (KiCad packages3D, STEP)
3D model files: tps79428dcqr-etched.step / tps79428dcqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps79428dcqr.step / tps79428dcqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (51 pp, sha256 84291eb77a7c37c6, retrieved 2026-10-11, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# TPS79428DCQR

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-223-6

TPS79428DCQR from Texas Instruments, in a SOT-223-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable input: a logic-high level enables the device and a logic-low level (below VEN(LOW), max 0.7 V for the old chip or 0.425 V for the new chip) puts it in shutdown, with VEN(HI) of at least 1.7 V (old chip) or 0.85 × VIN (new chip) and VEN up to 5.5 V. |
| 2 | IN | input | Unregulated input to the regulator, operating over 2.7 V to 5.5 V, with an absolute maximum of 6 V (old chip) or VIN + 0.3 V / 6.5 V, whichever is smaller (new chip), and a ceramic input bypass capacitor of at least 1 µF to GND. |
| 3 | GND | power_in | Regulator ground, which should connect directly to the bypass-capacitor grounds and be kept on its own ground plane for best PSRR and noise performance. |
| 4 | OUT | output | Regulator output, which requires a ceramic output capacitor of at least 1 µF (recommended 2.2 µF, with a minimum effective 0.47 µF on the new chip) between OUT and GND for loop stability. |
| 5 | NR/NC | input | On the old chip this is the noise-reduction pin, where an external capacitor of 0 to 100 nF (CNR, which must have minimal leakage) filters bandgap noise; on the new chip it is a no-connect pin that should be tied to GND or left floating. |
| 6 | GND | power_in | Ground pin that is also electrically tied to the SOT-223 thermal tab, which must be soldered to a large copper area on the board to dissipate heat. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-223-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |

## CAD (KiCad official)

- Symbol: `TPS79428DCQR`
- Footprint: `Package_TO_SOT_SMD:SOT-223-6`
- 3D model: SOT-223-6 (KiCad packages3D, STEP)
- 3D model files: `tps79428dcqr-etched.step` / `tps79428dcqr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps79428dcqr.step` / `tps79428dcqr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps794) (51 pp, sha256 `84291eb77a7c37c6`, retrieved 2026-10-11, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps79428dcqr-datasheet.pdf)